[dv] Fix timeout in rom_ctrl stress tests

Common tl_errors vseq wasn't passing custom 'tl_accesss_timeout_ns' task parameter to 'tl_access' which caused some timeouts in rom_ctrl tb. Pass it. Signed-off-by: Antonio Martinez Zambrana <[email protected]>
lowRISC · Jan 16, 2024 · fa5b861 · fa5b861
1 parent 890b751
commit fa5b861
Showing 1 changed file with 13 additions and 4 deletions.
diff --git a/hw/dv/sv/cip_lib/seq_lib/cip_base_vseq__tl_errors.svh b/hw/dv/sv/cip_lib/seq_lib/cip_base_vseq__tl_errors.svh
@@ -185,7 +185,10 @@ virtual task tl_instr_type_err(string ral_name);
     endcase
 
     tl_access(.addr(addr), .write(write), .data(data), .instr_type(instr_type), .exp_err_rsp(1),
-              .tl_sequencer_h(p_sequencer.tl_sequencer_hs[ral_name]));
+              .tl_sequencer_h(p_sequencer.tl_sequencer_hs[ral_name]),
+              .tl_access_timeout_ns(cfg.tl_access_timeout_ns)
+              );
+
   end
 endtask
 
@@ -345,7 +348,9 @@ virtual task issue_tl_access_w_intg_err(string ral_name);
   endcase
   tl_access(.addr(addr), .write(write), .data(data), .tl_intg_err_type(tl_intg_err_type),
             .mask(get_rand_contiguous_mask()),
-            .tl_sequencer_h(p_sequencer.tl_sequencer_hs[ral_name]));
+            .tl_sequencer_h(p_sequencer.tl_sequencer_hs[ral_name]),
+            .tl_access_timeout_ns(cfg.tl_access_timeout_ns)
+            );
 endtask
 
 virtual task check_tl_intg_error_response();
@@ -432,7 +437,9 @@ virtual task test_intg_err_in_passthru_mem(const ref dv_base_mem mems[$]);
     // Before inject faults, this read should have correct integrity
     tl_access_sub(.addr(addr), .write(0), .data(data), .completed(completed), .saw_err(saw_err),
                   .check_rsp(1),  .rsp(tl_access_rsp),
-                  .tl_sequencer_h(p_sequencer.tl_sequencer_hs[ral_name]));
+                  .tl_sequencer_h(p_sequencer.tl_sequencer_hs[ral_name]),
+                  .tl_access_timeout_ns(cfg.tl_access_timeout_ns)
+                  );
     `DV_CHECK_EQ(completed, 1)
     `DV_CHECK_EQ(saw_err, 0)
     void'(tl_access_rsp.is_d_chan_intg_ok(.en_rsp_intg_chk(1),
@@ -446,7 +453,9 @@ virtual task test_intg_err_in_passthru_mem(const ref dv_base_mem mems[$]);
     // Issue a read on the address that has been injected with integrity error
     tl_access_sub(.addr(addr), .write(0), .data(data), .completed(completed), .saw_err(saw_err),
                   .check_rsp(1),  .rsp(tl_access_rsp),
-                  .tl_sequencer_h(p_sequencer.tl_sequencer_hs[ral_name]));
+                  .tl_sequencer_h(p_sequencer.tl_sequencer_hs[ral_name]),
+                  .tl_access_timeout_ns(cfg.tl_access_timeout_ns)
+                  );
     `DV_CHECK_EQ(completed, 1)
     `DV_CHECK_EQ(saw_err, 0)
     // data integrity should be wrong