[prim] Remove primgen and replace with virtual cores #3766
Annotations
9 errors
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Countermeasures implemented (englishbreakfast)
Countermeasure check failed.
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Countermeasures implemented (englishbreakfast)
Process completed with exit code 1.
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Verible RTL
Verilog style lint of design sources with Verible failed. Run 'util/dvsim/dvsim.py -t veriblelint hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson' and fix all errors.
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Verible RTL
Process completed with exit code 1.
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Bazel target names
Some target names have banned characters.
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Bazel target names
Process completed with exit code 1.
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DV software images
Process completed with exit code 1.
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Countermeasures implemented (earlgrey)
Countermeasure check failed.
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Countermeasures implemented (earlgrey)
Process completed with exit code 1.
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