[prim] Remove primgen and replace with virtual cores #3766
a-willci.yml
on: pull_request
Lint (quick)
3m 1s
Earl Grey for CW310 Hyperdebug
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Build bitstream
1h 20m
Lint (slow)
8m 48s
Build documentation
5m 40s
Airgapped build
8m 13s
Verible lint
1m 54s
Run OTBN smoke Test
2m 19s
Run OTBN crypto tests
22m 26s
Verilated English Breakfast
8m 4s
Verilated Earl Grey
1h 24m
CW305's Bitstream
22m 2s
Build Docker Containers
3m 0s
Build and test software
22m 30s
CW340 Test ROM Tests
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FPGA test
5m 43s
CW340 ROM Tests
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FPGA test
1m 41s
CW340 ROM_EXT Tests
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FPGA test
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CW340 SiVal Tests
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FPGA test
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CW340 SiVal ROM_EXT Tests
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FPGA test
3m 47s
CW340 Manufacturing Tests
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FPGA test
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CW310 Test ROM Tests
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FPGA test
5m 28s
CW310 ROM Tests
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FPGA test
40m 24s
CW310 ROM_EXT Tests
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FPGA test
7m 54s
CW310 SiVal Tests
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FPGA test
27m 50s
CW310 SiVal ROM_EXT Tests
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FPGA test
35m 31s
CW310 Manufacturing Tests
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FPGA test
33m 28s
Cache bitstreams to GCP
0s
Verify FPGA jobs
29s
Annotations
12 errors
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Verilog style lint of design sources with Verible failed. Run 'util/dvsim/dvsim.py -t veriblelint hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson' and fix all errors.
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Some target names have banned characters.
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CW305's Bitstream
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Artifacts
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execute_manuf_fpga_tests_cw310-targets
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623 Bytes |
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execute_manuf_fpga_tests_cw310-test-results
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execute_manuf_fpga_tests_cw340-targets
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execute_manuf_fpga_tests_cw340-test-results
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execute_rom_ext_fpga_tests_cw310-targets
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519 Bytes |
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execute_rom_ext_fpga_tests_cw310-test-results
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execute_rom_ext_fpga_tests_cw340-targets
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437 Bytes |
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execute_rom_ext_fpga_tests_cw340-test-results
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7.33 KB |
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execute_rom_fpga_tests_cw310-targets
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execute_rom_fpga_tests_cw310-test-results
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execute_rom_fpga_tests_cw340-targets
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execute_rom_fpga_tests_cw340-test-results
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201 Bytes |
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execute_sival_fpga_tests_cw310-targets
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execute_sival_fpga_tests_cw310-test-results
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execute_sival_fpga_tests_cw340-targets
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502 Bytes |
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execute_sival_fpga_tests_cw340-test-results
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execute_sival_rom_ext_fpga_tests_cw310-targets
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execute_sival_rom_ext_fpga_tests_cw310-test-results
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181 KB |
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execute_sival_rom_ext_fpga_tests_cw340-targets
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435 Bytes |
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execute_sival_rom_ext_fpga_tests_cw340-test-results
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17.1 KB |
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execute_test_rom_fpga_tests_cw310-targets
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312 Bytes |
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execute_test_rom_fpga_tests_cw310-test-results
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2.94 KB |
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execute_test_rom_fpga_tests_cw340-targets
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258 Bytes |
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execute_test_rom_fpga_tests_cw340-test-results
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45.4 KB |
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partial-build-bin-chip_earlgrey_cw310
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5.98 MB |
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partial-build-bin-chip_earlgrey_cw310_hyperdebug
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6.01 MB |
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partial-build-bin-chip_earlgrey_cw340
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10.1 MB |
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sw_build_test-test-results
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74.7 KB |
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verilated_englishbreakfast
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6.25 MB |
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verilator_earlgrey-test-results
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8.95 KB |
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