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[fpga] Add prim features and tool flow to dump the flash info array cell sites #2936

[fpga] Add prim features and tool flow to dump the flash info array cell sites

[fpga] Add prim features and tool flow to dump the flash info array cell sites #2936

Triggered via pull request December 7, 2024 03:55
Status Cancelled
Total duration 13m 56s
Artifacts 1

ci.yml

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17 errors and 6 warnings
Verible lint
Process completed with exit code 1.
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Verible lint: hw/ip/prim_xilinx/rtl/prim_xilinx_pkg.sv#L7
[verible-verilog-lint] reported by reviewdog 🐶 Explicitly define static or automatic lifetime for non-class functions [Style: function-task-explicit-lifetime] [explicit-function-lifetime] Raw Output: message:"Explicitly define static or automatic lifetime for non-class functions [Style: function-task-explicit-lifetime] [explicit-function-lifetime]" location:{path:"./hw/ip/prim_xilinx/rtl/prim_xilinx_pkg.sv" range:{start:{line:7 column:16}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Verible lint: hw/ip/prim_xilinx/rtl/prim_xilinx_ram_1p.sv#L39
[verible-verilog-lint] reported by reviewdog 🐶 All generate block labels must start with g_ or gen_ [Style: generate-constructs] [generate-label-prefix] Raw Output: message:"All generate block labels must start with g_ or gen_ [Style: generate-constructs] [generate-label-prefix]" location:{path:"./hw/ip/prim_xilinx/rtl/prim_xilinx_ram_1p.sv" range:{start:{line:39 column:20}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Verible lint: hw/ip/prim_xilinx/rtl/prim_xilinx_ram_1p.sv#L46
[verible-verilog-lint] reported by reviewdog 🐶 All generate block labels must start with g_ or gen_ [Style: generate-constructs] [generate-label-prefix] Raw Output: message:"All generate block labels must start with g_ or gen_ [Style: generate-constructs] [generate-label-prefix]" location:{path:"./hw/ip/prim_xilinx/rtl/prim_xilinx_ram_1p.sv" range:{start:{line:46 column:65}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Verible lint: hw/ip/prim_xilinx/rtl/prim_xilinx_ram_1p.sv#L48
[verible-verilog-lint] reported by reviewdog 🐶 Explicitly define a storage type for every parameter and localparam, (PrimMemoryInitFile). [Style: constants] [explicit-parameter-storage-type] Raw Output: message:"Explicitly define a storage type for every parameter and localparam, (PrimMemoryInitFile). [Style: constants] [explicit-parameter-storage-type]" location:{path:"./hw/ip/prim_xilinx/rtl/prim_xilinx_ram_1p.sv" range:{start:{line:48 column:18}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Verible lint: hw/top_earlgrey/rtl/prim_xilinx_pkg.sv#L7
[verible-verilog-lint] reported by reviewdog 🐶 Explicitly define static or automatic lifetime for non-class functions [Style: function-task-explicit-lifetime] [explicit-function-lifetime] Raw Output: message:"Explicitly define static or automatic lifetime for non-class functions [Style: function-task-explicit-lifetime] [explicit-function-lifetime]" location:{path:"./hw/top_earlgrey/rtl/prim_xilinx_pkg.sv" range:{start:{line:7 column:16}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
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