[fpga] Add flow and constraints to dump the flash info array cell sites #2678

Job	Run time
Lint (quick)	2m 58s
Verible lint	1m 2s
Lint (slow)	13m 49s
Run OTBN crypto tests	2m 34s
Airgapped build	9m 16s
CW305's Bitstream	24m 34s
Run OTBN smoke Test	2m 31s
Verilated Earl Grey	1h 16m 8s
Verilated English Breakfast	8m 58s
Build Docker Containers	2m 44s
Build and test software	14m 52s
Earl Grey for CW310 / Build bitstream	1h 20m 10s
Earl Grey for CW310 Hyperdebug / Build bitstream	1h 8m 54s
Earl Grey for CW340 / Build bitstream	1h 30m 39s
CW310 Manufacturing Tests / FPGA test	32m 40s
CW310 SiVal Tests / FPGA test	24m 40s
CW310 SiVal ROM_EXT Tests / FPGA test	35m 55s
CW310 ROM Tests / FPGA test	38m 31s
CW310 ROM_EXT Tests / FPGA test	8m 8s
CW310 Test ROM Tests / FPGA test	4m 43s
Cache bitstreams to GCP	0s
CW340 ROM Tests / FPGA test	56s
CW340 Test ROM Tests / FPGA test	7m 20s
CW340 Manufacturing Tests / FPGA test	6m 41s
CW340 ROM_EXT Tests / FPGA test	3m 31s
CW340 SiVal Tests / FPGA test	15m 25s
CW340 SiVal ROM_EXT Tests / FPGA test	3m 53s
Verify FPGA jobs	34s
	9h 42m 6s

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