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[fpga] Add flow and constraints to dump the flash info array cell sites #2678

[fpga] Add flow and constraints to dump the flash info array cell sites

[fpga] Add flow and constraints to dump the flash info array cell sites #2678

Earl Grey for CW310 Hyperdebug  /  Build bitstream

succeeded Nov 30, 2024 in 1h 8m 54s
Set up job
1s
Run actions/checkout@v4
9s
Prepare environment
22s
Configure bitstream strategy
1m 30s
Extract cached bitstream
0s
Build and splice bitstream with Vivado
1h 6m 48s
Display synthesis & implementation logs
0s
Upload step outputs
1s
Upload artifacts if build failed
0s
Post Prepare environment
0s
Post Run actions/checkout@v4
0s
Complete job
0s