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Mem response agent fix #2177

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Jun 21, 2024
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11 changes: 11 additions & 0 deletions doc/03_reference/coverage_plan.rst
Original file line number Diff line number Diff line change
Expand Up @@ -375,6 +375,17 @@ The mapping between security countermeasures and coverpoints that demonstrate it
| ICACHE.MEM.INTEGRITY | ``cp_icache_ecc_err`` |
+--------------------------------+-------------------------------------------------------+

Memory Interface Behaviour
^^^^^^^^^^^^^^^^^^^^^^^^^^
Covering different scenarios around timing of memory requests and responses and
related behaviour

* ``cp_dmem_response_latency``/``cp_imem_response_latency`` - Latency of response from request for dmem and imem.
Separated into two bins ``single_cycle`` (immediate response after request) and ``multi_cycle`` (all other latencies).
* ``dmem_req_gnt_valid``/``imem_req_gnt_rvalid`` - Request, grant and rvalid all seen in the same cycle for dmem and imem.
This means a response is seen the same cycle a new request is being granted.


Miscellaneous
^^^^^^^^^^^^^
Various points of interest do not fit into the categories above.
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -54,7 +54,7 @@ class ibex_mem_intf_monitor extends uvm_monitor;
ibex_mem_intf_seq_item trans_collected;
forever begin
trans_collected = ibex_mem_intf_seq_item::type_id::create("trans_collected");
while(!(vif.monitor_cb.request && vif.monitor_cb.grant)) vif.wait_clks(1);
while(!(vif.monitor_cb.request && vif.monitor_cb.grant)) @(vif.monitor_cb);
trans_collected.addr = vif.monitor_cb.addr;
trans_collected.be = vif.monitor_cb.be;
trans_collected.misaligned_first = vif.monitor_cb.misaligned_first;
Expand All @@ -71,7 +71,7 @@ class ibex_mem_intf_monitor extends uvm_monitor;
addr_ph_port.write(trans_collected);
`uvm_info(get_full_name(),"Send through addr_ph_port", UVM_HIGH)
collect_response_queue.put(trans_collected);
vif.wait_clks(1);
@(vif.monitor_cb);
end
endtask : collect_address_phase

Expand All @@ -80,7 +80,7 @@ class ibex_mem_intf_monitor extends uvm_monitor;
forever begin
collect_response_queue.get(trans_collected);
do
vif.wait_clks(1);
@(vif.monitor_cb);
while(vif.monitor_cb.rvalid === 0);

if (trans_collected.read_write == READ) begin
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -66,7 +66,7 @@ class ibex_mem_intf_response_driver extends uvm_driver #(ibex_mem_intf_seq_item)
begin
forever begin
ibex_mem_intf_seq_item req, req_c;
cfg.vif.wait_clks(1);
@(cfg.vif.response_driver_cb);
seq_item_port.get_next_item(req);
$cast(req_c, req.clone());
if(~cfg.vif.response_driver_cb.reset) begin
Expand Down Expand Up @@ -112,14 +112,16 @@ class ibex_mem_intf_response_driver extends uvm_driver #(ibex_mem_intf_seq_item)
virtual protected task send_read_data();
ibex_mem_intf_seq_item tr;
forever begin
cfg.vif.wait_clks(1);
@(cfg.vif.response_driver_cb);
cfg.vif.response_driver_cb.rvalid <= 1'b0;
cfg.vif.response_driver_cb.rdata <= 'x;
cfg.vif.response_driver_cb.rintg <= 'x;
cfg.vif.response_driver_cb.error <= 'x;
rdata_queue.get(tr);
if(cfg.vif.response_driver_cb.reset) continue;
cfg.vif.wait_clks(tr.rvalid_delay);

repeat (tr.rvalid_delay) @(cfg.vif.response_driver_cb);

if(~cfg.vif.response_driver_cb.reset) begin
cfg.vif.response_driver_cb.rvalid <= 1'b1;
cfg.vif.response_driver_cb.error <= tr.error;
Expand Down
85 changes: 84 additions & 1 deletion dv/uvm/core_ibex/fcov/core_ibex_fcov_if.sv
Original file line number Diff line number Diff line change
Expand Up @@ -20,7 +20,15 @@ interface core_ibex_fcov_if import ibex_pkg::*; (
input fcov_rf_ecc_err_a_id,
input fcov_rf_ecc_err_b_id,

input ibex_mubi_t fetch_enable_i
input ibex_mubi_t fetch_enable_i,

input instr_req_o,
input instr_gnt_i,
input instr_rvalid_i,

input data_req_o,
input data_gnt_i,
input data_rvalid_i
);
`include "dv_fcov_macros.svh"
import uvm_pkg::*;
Expand Down Expand Up @@ -390,6 +398,28 @@ interface core_ibex_fcov_if import ibex_pkg::*; (
logic rf_we_glitch_err;
logic lockstep_glitch_err;

logic imem_single_cycle_response, dmem_single_cycle_response;

mem_monitor_if iside_mem_monitor(
.clk_i,
.rst_ni,
.req_i(instr_req_o),
.gnt_i(instr_gnt_i),
.rvalid_i(instr_rvalid_i),
.outstanding_requests_o(),
.single_cycle_response_o(imem_single_cycle_response)
);

mem_monitor_if dside_mem_monitor(
.clk_i,
.rst_ni,
.req_i(data_req_o),
.gnt_i(data_gnt_i),
.rvalid_i(data_rvalid_i),
.outstanding_requests_o(),
.single_cycle_response_o(dmem_single_cycle_response)
);

covergroup uarch_cg @(posedge clk_i);
option.per_instance = 1;
option.name = "uarch_cg";
Expand Down Expand Up @@ -613,6 +643,20 @@ interface core_ibex_fcov_if import ibex_pkg::*; (
cp_misaligned_second_data_bus_err: coverpoint load_store_unit_i.data_bus_err_i iff
(load_store_unit_i.fcov_mis_rvalid_2);

cp_imem_response_latency: coverpoint imem_single_cycle_response iff (instr_rvalid_i) {
bins single_cycle = {1'b1};
bins multi_cycle = {1'b0};
}

`DV_FCOV_EXPR_SEEN(imem_req_gnt_rvalid, instr_rvalid_i & instr_req_o & instr_gnt_i)

cp_dmem_response_latency: coverpoint dmem_single_cycle_response iff (data_rvalid_i) {
bins single_cycle = {1'b1};
bins multi_cycle = {1'b0};
}

`DV_FCOV_EXPR_SEEN(dmem_req_gnt_rvalid, data_rvalid_i & data_req_o & data_gnt_i)

misaligned_data_bus_err_cross: cross cp_misaligned_first_data_bus_err,
cp_misaligned_second_data_bus_err {
// Cannot see both bus errors together as they're signalled at different states of the load
Expand Down Expand Up @@ -766,3 +810,42 @@ interface core_ibex_fcov_if import ibex_pkg::*; (

`DV_FCOV_INSTANTIATE_CG(uarch_cg, en_uarch_cov)
endinterface

interface mem_monitor_if (
input clk_i,
input rst_ni,

input req_i,
input gnt_i,
input rvalid_i,

output int outstanding_requests_o,
output logic single_cycle_response_o
);

int outstanding_requests;
logic outstanding_requests_inc, outstanding_requests_dec;
logic no_outstanding_requests_last_cycle;

assign outstanding_requests_inc = req_i & gnt_i;
assign outstanding_requests_dec = rvalid_i;

always_ff @(posedge clk_i or negedge rst_ni) begin
if (~rst_ni) begin
outstanding_requests <= 0;
no_outstanding_requests_last_cycle <= 1'b0;
end else begin
if (outstanding_requests_inc && !outstanding_requests_dec) begin
outstanding_requests <= outstanding_requests + 1;
end else if (!outstanding_requests_inc && outstanding_requests_dec) begin
outstanding_requests <= outstanding_requests - 1;
end

no_outstanding_requests_last_cycle <= (outstanding_requests == 0) ||
((outstanding_requests == 1) && outstanding_requests_dec);
end
end

assign outstanding_requests_o = outstanding_requests;
assign single_cycle_response_o = no_outstanding_requests_last_cycle & rvalid_i;
endinterface
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