[dv] Increase iterations and instructions in riscv_rf_intg_test

This enables more scenarios begin stimulated per regression run around RF ECC errors.
lowRISC · Jul 15, 2024 · 96a1c02 · 96a1c02
1 parent 6ac0ddc
commit 96a1c02
Showing 1 changed file with 7 additions and 1 deletion.
diff --git a/dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml b/dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml
@@ -683,8 +683,14 @@
 - test: riscv_rf_intg_test
   description: >
     Randomly corrupt the register file read port once in the middle of program execution
-  iterations: 15
+  iterations: 100
   gen_test: riscv_rand_instr_test
+  gen_opts: >
+    +instr_cnt=10000
+    +num_of_sub_program=5
+    +gen_all_csrs_by_default=1
+    +add_csr_write=MSTATUS,MEPC,MCAUSE,MTVAL,0x7c0,0x7c1
+    +no_csr_instr=0
   rtl_test: core_ibex_rf_intg_test
   rtl_params:
     SecureIbex: 1