[dv] Alter riscv_rf_intg_test to cover more scenarios

Previously the riscv_rf_intg_test skipped certain scenarios where an ECC error from the register file should trigger an alert. This change stops it from skipping those scenarios.
lowRISC · Jul 15, 2024 · 6ac0ddc · 6ac0ddc
1 parent 9e4a950
commit 6ac0ddc
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Showing 3 changed files with 13 additions and 3 deletions.
diff --git a/dv/uvm/core_ibex/env/core_ibex_dut_probe_if.sv b/dv/uvm/core_ibex/env/core_ibex_dut_probe_if.sv
@@ -34,6 +34,7 @@ interface core_ibex_dut_probe_if(input logic clk);
   logic                              rf_ren_b;
   logic                              rf_rd_a_wb_match;
   logic                              rf_rd_b_wb_match;
+  logic                              rf_write_wb;
   logic                              sync_exc_seen;
   logic                              irq_exc_seen;
   logic                              csr_save_cause;
@@ -80,6 +81,7 @@ interface core_ibex_dut_probe_if(input logic clk);
     input rf_ren_b;
     input rf_rd_a_wb_match;
     input rf_rd_b_wb_match;
+    input rf_write_wb;
     input sync_exc_seen;
     input irq_exc_seen;
     input wb_exception;
@@ -93,6 +95,7 @@ interface core_ibex_dut_probe_if(input logic clk);
   `DV_CREATE_SIGNAL_PROBE_FUNCTION(signal_probe_rf_ren_b, rf_ren_b)
   `DV_CREATE_SIGNAL_PROBE_FUNCTION(signal_probe_rf_rd_a_wb_match, rf_rd_a_wb_match)
   `DV_CREATE_SIGNAL_PROBE_FUNCTION(signal_probe_rf_rd_b_wb_match, rf_rd_b_wb_match)
+  `DV_CREATE_SIGNAL_PROBE_FUNCTION(signal_probe_rf_write_wb, rf_write_wb)
   `DV_CREATE_SIGNAL_PROBE_FUNCTION(signal_probe_alert_minor, alert_minor)
   `DV_CREATE_SIGNAL_PROBE_FUNCTION(signal_probe_ic_tag_req, ic_tag_req)
   `DV_CREATE_SIGNAL_PROBE_FUNCTION(signal_probe_ic_tag_write, ic_tag_write)

diff --git a/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv b/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv
@@ -250,6 +250,7 @@ module core_ibex_tb_top;
   assign dut_if.rf_ren_b         = dut.u_ibex_top.u_ibex_core.rf_ren_b;
   assign dut_if.rf_rd_a_wb_match = dut.u_ibex_top.u_ibex_core.rf_rd_a_wb_match;
   assign dut_if.rf_rd_b_wb_match = dut.u_ibex_top.u_ibex_core.rf_rd_b_wb_match;
+  assign dut_if.rf_write_wb      = dut.u_ibex_top.u_ibex_core.rf_write_wb;
   assign dut_if.sync_exc_seen    = dut.u_ibex_top.u_ibex_core.cs_registers_i.cpuctrlsts_part_q.sync_exc_seen;
   assign dut_if.csr_save_cause   = dut.u_ibex_top.u_ibex_core.csr_save_cause;
   assign dut_if.exc_cause        = dut.u_ibex_top.u_ibex_core.exc_cause;

diff --git a/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv b/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv
@@ -129,7 +129,8 @@ class core_ibex_rf_intg_test extends core_ibex_base_test;
   endfunction
 
   virtual task send_stimulus();
-    bit port_idx;
+    int    rnd_delay;
+    bit    port_idx;
     string port_name;
 
     vseq.start(env.vseqr);
@@ -138,14 +139,19 @@ class core_ibex_rf_intg_test extends core_ibex_base_test;
     port_idx = $urandom_range(1);
     port_name = port_idx ? "rf_rdata_b_ecc" : "rf_rdata_a_ecc";
 
+    `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(rnd_delay, rnd_delay > 1000; rnd_delay < 10_000;)
+    clk_vif.wait_n_clks(rnd_delay);
+
     forever begin
-      logic rf_ren, rf_rd_wb_match;
+      logic rf_ren, rf_rd_wb_match, rf_write_wb;
       int unsigned bit_idx;
       uvm_hdl_data_t data, mask;
       logic exp_alert, alert_major_internal;
 
       clk_vif.wait_n_clks(1);
 
+      rf_write_wb = dut_vif.signal_probe_rf_write_wb(dv_utils_pkg::SignalProbeSample);
+
       // Check if port is being read.
       if (port_idx) begin
         rf_ren = dut_vif.signal_probe_rf_ren_b(dv_utils_pkg::SignalProbeSample);
@@ -156,7 +162,7 @@ class core_ibex_rf_intg_test extends core_ibex_base_test;
       end
 
       // Only corrupt port if it is read.
-      if (!(rf_ren == 1'b1 && rf_rd_wb_match == 1'b0)) continue;
+      if (!(rf_ren == 1'b1 && (rf_rd_wb_match == 1'b0 || rf_write_wb == 1'b0))) continue;
 
       data = read_data(port_name);
       `uvm_info(`gfn, $sformatf("Corrupting %s; original value: 'h%0x", port_name, data), UVM_LOW)