SYNCHRONOUS FIFO TESTBENCH

Getting familiar with SystemVerilog and UVM Testbenches
Device Under Test (DUT) is a single-clock Register-based FIFO
The circular buffer has a maximum capacity of 16, with an active LOW Reset
Has Enable signals for READ and WRITE operations, and flags to determine EMPTY and FULL status
Made reusable testbench components like sequences, drivers, monitors, agents

Name		Name	Last commit message	Last commit date
Latest commit History 27 Commits
LICENSE		LICENSE
README.md		README.md
agent.sv		agent.sv
coverage.sv		coverage.sv
design.sv		design.sv
driver.sv		driver.sv
fifo_pkg.sv		fifo_pkg.sv
monitor.sv		monitor.sv
scoreboard.sv		scoreboard.sv
sequencer.sv		sequencer.sv
tests_top.sv		tests_top.sv
top_testbench.sv		top_testbench.sv
transaction.sv		transaction.sv

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