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[TritonGEN] Use OCL builtins for subgroup block read/write #2178

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merged 6 commits into from
Sep 11, 2024
Merged

[TritonGEN] Use OCL builtins for subgroup block read/write #2178

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412d102
[TritonGEN] Use OCL builtins for subgroup block read/write
whitneywhtsang Sep 10, 2024
65a4b43
address review comments
whitneywhtsang Sep 11, 2024
2494e1c
Merge remote-tracking branch 'origin/llvm-target' into whitneywhtsang…
whitneywhtsang Sep 11, 2024
85f3601
Merge branch 'llvm-target' into whitneywhtsang/simdblock
whitneywhtsang Sep 11, 2024
e49287c
Disallow 16xi16 for now
whitneywhtsang Sep 11, 2024
142feba
Use constexpr
whitneywhtsang Sep 11, 2024
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11 changes: 6 additions & 5 deletions test/Conversion/intel/tritongpu_to_llvm_intel_advanced_path.mlir
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Expand Up @@ -281,11 +281,12 @@ module attributes {"triton_gpu.num-warps" = 4 : i32, "triton_gpu.threads-per-war
// CHECK: %[[VAL_7:.*]] = llvm.mlir.constant(256 : i64) : i64
// CHECK: %[[VAL_8:.*]] = llvm.mul %[[VAL_7]], %[[VAL_3]] : i64
// CHECK: %[[VAL_9:.*]] = llvm.getelementptr inbounds %[[VAL_0]]{{\[}}%[[VAL_8]]] : (!llvm.ptr<3>, i64) -> !llvm.ptr<3>, f32
// CHECK: llvm.call spir_funccc @llvm.genx.GenISA.simdBlockWrite(%[[VAL_9]], %[[VAL_1]]) {{{.*}}} : (!llvm.ptr<3>, vector<16xf32>) -> ()
// CHECK: %[[VAL_10:.*]] = llvm.mul %[[VAL_6]], %[[VAL_5]] : i64
// CHECK: %[[VAL_11:.*]] = llvm.getelementptr inbounds %[[VAL_9]]{{\[}}%[[VAL_10]]] : (!llvm.ptr<3>, i64) -> !llvm.ptr<3>, f32
// CHECK: %[[VAL_12:.*]] = llvm.load %[[VAL_11]] : !llvm.ptr<3> -> vector<16xf32>
// CHECK: llvm.return %[[VAL_12]] : vector<16xf32>
// CHECK: %[[VAL_10:.*]] = llvm.bitcast %[[VAL_1]] : vector<16xf32> to vector<16xi32>
// CHECK: llvm.call spir_funccc @llvm.genx.GenISA.simdBlockWrite(%[[VAL_9]], %[[VAL_10]]) {{{.*}}} : (!llvm.ptr<3>, vector<16xi32>) -> ()
// CHECK: %[[VAL_11:.*]] = llvm.mul %[[VAL_6]], %[[VAL_5]] : i64
// CHECK: %[[VAL_12:.*]] = llvm.getelementptr inbounds %[[VAL_9]]{{\[}}%[[VAL_11]]] : (!llvm.ptr<3>, i64) -> !llvm.ptr<3>, f32
// CHECK: %[[VAL_13:.*]] = llvm.load %[[VAL_12]] : !llvm.ptr<3> -> vector<16xf32>
// CHECK: llvm.return %[[VAL_13]] : vector<16xf32>
tt.func @test(%arg0: !tt.ptr<f32, 3>, %arg1: tensor<16x16xf32>) -> tensor<16x16xf32> {
%0 = triton_intel_gpu.sub_group_transpose %arg0, %arg1 : tensor<16x16xf32>
tt.return %0 : tensor<16x16xf32>
Expand Down
22 changes: 22 additions & 0 deletions test/TritonGEN/tritongen-to-llvm.mlir
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Expand Up @@ -289,6 +289,17 @@ llvm.func @triton_gen.simdblockread(%ptr: !llvm.ptr<3>) {

// -----

// CHECK: llvm.func spir_funccc @_Z30intel_sub_group_block_read_us2PU3AS3t(!llvm.ptr<3>) -> vector<2xi16> attributes {passthrough = ["nofree", "nounwind", "willreturn", ["memory", "1"]]}

llvm.func @triton_gen.simdblockread(%ptr: !llvm.ptr<3>) {
// CHECK: llvm.func @triton_gen.simdblockread(%arg0: !llvm.ptr<3>) {
// CHECK: llvm.call spir_funccc @_Z30intel_sub_group_block_read_us2PU3AS3t(%arg0) {{.*}} : (!llvm.ptr<3>) -> vector<2xi16>
%ret = triton_gen.simdblockread %ptr : (!llvm.ptr<3>) -> vector<2xi16>
llvm.return
}

// -----

// CHECK: llvm.func spir_funccc @llvm.genx.GenISA.simdBlockWrite(!llvm.ptr<3>, vector<64xi16>) attributes {passthrough = ["nofree", "nounwind", "willreturn", ["memory", "3"]]}

llvm.func @triton_gen.simdblockwrite(%ptr: !llvm.ptr<3>, %val : vector<64xi16>) {
Expand All @@ -297,3 +308,14 @@ llvm.func @triton_gen.simdblockwrite(%ptr: !llvm.ptr<3>, %val : vector<64xi16>)
triton_gen.simdblockwrite %ptr, %val : (!llvm.ptr<3>, vector<64xi16>)
llvm.return
}

// -----

// CHECK: llvm.func spir_funccc @_Z31intel_sub_group_block_write_us2PU3AS3tDv2_t(!llvm.ptr<3>, vector<2xi16>) attributes {passthrough = ["nofree", "nounwind", "willreturn", ["memory", "3"]]}

llvm.func @triton_gen.simdblockwrite(%ptr: !llvm.ptr<3>, %val : vector<2xi16>) {
// CHECK: llvm.func @triton_gen.simdblockwrite(%arg0: !llvm.ptr<3>, %arg1: vector<2xi16>) {
// CHECK: llvm.call spir_funccc @_Z31intel_sub_group_block_write_us2PU3AS3tDv2_t(%arg0, %arg1) {{.*}} : (!llvm.ptr<3>, vector<2xi16>) -> ()
triton_gen.simdblockwrite %ptr, %val : (!llvm.ptr<3>, vector<2xi16>)
llvm.return
}
4 changes: 2 additions & 2 deletions third_party/intel/include/Dialect/TritonGEN/IR/TritonGENOps.td
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Expand Up @@ -397,7 +397,7 @@ def TritonGEN_Matrix2DBlockPrefetchOp : TritonGEN_Op<"2Dblockprefetch">,
}

def TritonGEN_SIMDBlockReadOp: TritonGEN_Op<"simdblockread">,
Results<(outs FixedVectorOf<[TritonGEN_MatrixElemType]>:$res)>,
Results<(outs FixedVectorOf<[AnyTypeOf<[AnyI8, AnyI16, AnyI32, AnyI64]>]>:$res)>,
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Arguments<(ins
Arg<LLVM_AnyPointer, "", [MemRead]>:$ptr
)> {
Expand All @@ -418,7 +418,7 @@ def TritonGEN_SIMDBlockReadOp: TritonGEN_Op<"simdblockread">,
def TritonGEN_SIMDBlockWriteOp : TritonGEN_Op<"simdblockwrite">,
Arguments<(ins
Arg<LLVM_AnyPointer, "", [MemWrite]>:$ptr,
FixedVectorOf<[TritonGEN_MatrixElemType]>:$val
FixedVectorOf<[AnyTypeOf<[AnyI8, AnyI16, AnyI32, AnyI64]>]>:$val
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)> {

let summary = "simd block write";
Expand Down
36 changes: 34 additions & 2 deletions third_party/intel/lib/TritonGENToLLVM/TritonGENToLLVMPass.cpp
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Expand Up @@ -1254,6 +1254,18 @@ struct TritonMatrix2DBlockPrefetchLowering
}
};

static bool isTySIMDOCLBuiltinAvailable(VectorType vecTy) {
unsigned numElems = vecTy.getNumElements();
if (numElems == 1 || numElems == 2 || numElems == 4 || numElems == 8)
return true;

IntegerType elemTy = cast<IntegerType>(vecTy.getElementType());
if ((elemTy.getWidth() == 8 || elemTy.getWidth() == 16) && numElems == 16)
return true;
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return false;
}

struct TritonSIMDBlockReadLowering
: public ConvertOpToLLVMPattern<TritonGEN::SIMDBlockReadOp> {
using ConvertOpToLLVMPattern<
Expand All @@ -1266,7 +1278,16 @@ struct TritonSIMDBlockReadLowering
VectorType vecTy = op.getRes().getType();

// TODO: Remove GenISA lowering after PoC productization is completed.
const StringLiteral funcName = "llvm.genx.GenISA.simdBlockRead";
std::string funcName = "llvm.genx.GenISA.simdBlockRead";
if (isTySIMDOCLBuiltinAvailable(vecTy)) {
unsigned numElems = vecTy.getNumElements();
funcName = "intel_sub_group_block_read_u" +
intel::getTypeMangling(vecTy.getElementType(), false) +
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(numElems == 1 ? "" : std::to_string(numElems));
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funcName = "_Z" + std::to_string(funcName.size()) + funcName + "PU3AS" +
std::to_string(ptrTy.getAddressSpace()) +
intel::getTypeMangling(vecTy.getElementType(), true);
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}

intel::AttributeList attrs = createFunctionAttributes(
{{llvm::Attribute::NoUnwind, std::nullopt},
Expand Down Expand Up @@ -1296,7 +1317,18 @@ struct TritonSIMDBlockWriteLowering
VectorType vecTy = op.getVal().getType();

// TODO: Remove GenISA lowering after PoC productization is completed.
const StringLiteral funcName = "llvm.genx.GenISA.simdBlockWrite";
std::string funcName = "llvm.genx.GenISA.simdBlockWrite";
if (isTySIMDOCLBuiltinAvailable(vecTy)) {
unsigned numElems = vecTy.getNumElements();
funcName = "intel_sub_group_block_write_u" +
intel::getTypeMangling(vecTy.getElementType(), false) +
(numElems == 1 ? "" : std::to_string(numElems));
funcName = "_Z" + std::to_string(funcName.size()) + funcName + "PU3AS" +
std::to_string(ptrTy.getAddressSpace()) +
intel::getTypeMangling(vecTy.getElementType(), true) +
intel::getTypeMangling(vecTy, true);
}
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intel::AttributeList attrs = createFunctionAttributes(
{{llvm::Attribute::NoUnwind, std::nullopt},
{llvm::Attribute::WillReturn, std::nullopt},
Expand Down
11 changes: 8 additions & 3 deletions third_party/intel/lib/TritonIntelGPUToLLVM/TritonOpsToLLVM.cpp
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Expand Up @@ -278,8 +278,6 @@ class LoadStorePrefetchOpConversion
base = gep(ptrToSharedMemTy, i16_ty, base, index);

if constexpr (std::is_same_v<OpType, LoadOp>) {
VectorType v64f16Ty = VectorType::get(64, f16_ty);

rewriter.restoreInsertionPoint(insertPoint);

TritonGEN::SIMDBlockReadOp simdRead =
Expand Down Expand Up @@ -618,7 +616,14 @@ class SubGroupTransposeOpConversion
ValueRange{subGroupOffset}, /*inbounds=*/true);

// Store matrix in local memory.
rewriter.create<TritonGEN::SIMDBlockWriteOp>(loc, subGroupBasePtr, src);
Value val =
vecTy.getElementType().isInteger()
? src
: bitcast(
src,
vec_ty(int_ty(vecTy.getElementType().getIntOrFloatBitWidth()),
vecTy.getNumElements()));
rewriter.create<TritonGEN::SIMDBlockWriteOp>(loc, subGroupBasePtr, val);

// Load from matrix, trasposed.
Value workItemOffset = mul(wiStride, subGroupLocalId);
Expand Down
2 changes: 1 addition & 1 deletion third_party/intel/lib/Utils/Mangling.cpp
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Expand Up @@ -20,7 +20,7 @@ std::string getTypeMangling(Type ty, bool isUnsigned) {
.Case([isUnsigned](IntegerType ty) -> std::string {
switch (ty.getWidth()) {
case 8:
return "c";
return isUnsigned ? "c" : "h";
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case 16:
return isUnsigned ? "t" : "s";
case 32:
Expand Down