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[TritonGEN] Use OCL builtins for subgroup block read/write #2178

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merged 6 commits into from
Sep 11, 2024

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@whitneywhtsang whitneywhtsang requested review from etiotto, quintinwang5 and a team September 10, 2024 02:42
@whitneywhtsang whitneywhtsang self-assigned this Sep 10, 2024
@whitneywhtsang whitneywhtsang force-pushed the whitneywhtsang/simdblock branch from 4dd8442 to 46ff791 Compare September 10, 2024 04:25
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@victor-eds victor-eds left a comment

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We can emulate wider vectors with several calls and avoid relying on GenISA intrinsics:

%res = triton_gen.simdblockread %ptr : (!llvm.ptr) -> vector<32xi32>

is equivalent to:

%0 = triton_gen.simdblockread %ptr : (!llvm.ptr) -> vector<8xi32>
%ptr1 = llvm.getelementptr inbounds %ptr[16] : (!llvm.ptr) -> !llvm.ptr, vector<8xi32>
%1 = triton_gen.simdblockread %ptr1 : (!llvm.ptr) -> vector<8xi32>
%ptr2 = llvm.getelementptr inbounds %ptr1[16] : (!llvm.ptr) -> !llvm.ptr, vector<8xi32>
%2 = triton_gen.simdblockread %ptr2 : (!llvm.ptr) -> vector<8xi32>
%ptr3 = llvm.getelementptr inbounds %ptr2[16] : (!llvm.ptr) -> !llvm.ptr, vector<8xi32>
%3 = triton_gen.simdblockread %ptr3 : (!llvm.ptr) -> vector<8xi32>
%res = // Vector concatenation %0 %1 %2 %3

@whitneywhtsang
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We can emulate wider vectors with several calls and avoid relying on GenISA intrinsics:

%res = triton_gen.simdblockread %ptr : (!llvm.ptr) -> vector<32xi32>

is equivalent to:

%0 = triton_gen.simdblockread %ptr : (!llvm.ptr) -> vector<8xi32>
%ptr1 = llvm.getelementptr inbounds %ptr[16] : (!llvm.ptr) -> !llvm.ptr, vector<8xi32>
%1 = triton_gen.simdblockread %ptr1 : (!llvm.ptr) -> vector<8xi32>
%ptr2 = llvm.getelementptr inbounds %ptr1[16] : (!llvm.ptr) -> !llvm.ptr, vector<8xi32>
%2 = triton_gen.simdblockread %ptr2 : (!llvm.ptr) -> vector<8xi32>
%ptr3 = llvm.getelementptr inbounds %ptr2[16] : (!llvm.ptr) -> !llvm.ptr, vector<8xi32>
%3 = triton_gen.simdblockread %ptr3 : (!llvm.ptr) -> vector<8xi32>
%res = // Vector concatenation %0 %1 %2 %3

Right, I have a local change for that, would like to do that in a separate PR.

@quintinwang5
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We can emulate wider vectors with several calls and avoid relying on GenISA intrinsics:

%res = triton_gen.simdblockread %ptr : (!llvm.ptr) -> vector<32xi32>

is equivalent to:

%0 = triton_gen.simdblockread %ptr : (!llvm.ptr) -> vector<8xi32>
%ptr1 = llvm.getelementptr inbounds %ptr[16] : (!llvm.ptr) -> !llvm.ptr, vector<8xi32>
%1 = triton_gen.simdblockread %ptr1 : (!llvm.ptr) -> vector<8xi32>
%ptr2 = llvm.getelementptr inbounds %ptr1[16] : (!llvm.ptr) -> !llvm.ptr, vector<8xi32>
%2 = triton_gen.simdblockread %ptr2 : (!llvm.ptr) -> vector<8xi32>
%ptr3 = llvm.getelementptr inbounds %ptr2[16] : (!llvm.ptr) -> !llvm.ptr, vector<8xi32>
%3 = triton_gen.simdblockread %ptr3 : (!llvm.ptr) -> vector<8xi32>
%res = // Vector concatenation %0 %1 %2 %3

Right, I have a local change for that, would like to do that in a separate PR.

How about its performance?

@whitneywhtsang
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We can emulate wider vectors with several calls and avoid relying on GenISA intrinsics:

%res = triton_gen.simdblockread %ptr : (!llvm.ptr) -> vector<32xi32>

is equivalent to:

%0 = triton_gen.simdblockread %ptr : (!llvm.ptr) -> vector<8xi32>
%ptr1 = llvm.getelementptr inbounds %ptr[16] : (!llvm.ptr) -> !llvm.ptr, vector<8xi32>
%1 = triton_gen.simdblockread %ptr1 : (!llvm.ptr) -> vector<8xi32>
%ptr2 = llvm.getelementptr inbounds %ptr1[16] : (!llvm.ptr) -> !llvm.ptr, vector<8xi32>
%2 = triton_gen.simdblockread %ptr2 : (!llvm.ptr) -> vector<8xi32>
%ptr3 = llvm.getelementptr inbounds %ptr2[16] : (!llvm.ptr) -> !llvm.ptr, vector<8xi32>
%3 = triton_gen.simdblockread %ptr3 : (!llvm.ptr) -> vector<8xi32>
%res = // Vector concatenation %0 %1 %2 %3

Right, I have a local change for that, would like to do that in a separate PR.

How about its performance?

I would like to test its performance, but the SLM path is not working at the moment, so I cannot get a baseline.

@whitneywhtsang whitneywhtsang marked this pull request as ready for review September 11, 2024 05:05
@Dewei-Wang-sh
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anywhere to document what the current ocl built-ins we can use in triton?

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@victor-eds victor-eds left a comment

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Small NIT. LGTM.

@vlad-penkin vlad-penkin linked an issue Sep 11, 2024 that may be closed by this pull request
@whitneywhtsang
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anywhere to document what the current ocl built-ins we can use in triton?

We can use any ocl built-ins documented in any OpenCL C extensions, if we want to use an OpenCL C builtin that is not available in any OpenCL C extensions, then we need to send a request to IGC team.

Signed-off-by: Whitney Tsang <[email protected]>
@whitneywhtsang whitneywhtsang enabled auto-merge (squash) September 11, 2024 15:54
@whitneywhtsang whitneywhtsang merged commit 5481995 into llvm-target Sep 11, 2024
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@whitneywhtsang whitneywhtsang deleted the whitneywhtsang/simdblock branch September 11, 2024 16:21
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[TritonGEN] Use OCL builtins for subgroup block read/write
5 participants