Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq

- fsl-qoriq: Bug fixes related pfe, eth, thermal node, vid.c, cpu release,
  mmc, usb, env, etc for Layerscape boards
- powerpc: Update Maintainers for some boards.

arch/arm/Kconfig

@@ -1491,6 +1491,24 @@ config TARGET_PG_WCOM_SELI8
 	 SELI8 is a QorIQ LS1021a based service unit card used
 	 in XMC20 and FOX615 product families.
 
+config TARGET_PG_WCOM_EXPU1
+	bool "Support Hitachi-Powergrids EXPU1 service unit card"
+	select ARCH_LS1021A
+	select ARCH_SUPPORT_PSCI
+	select BOARD_EARLY_INIT_F
+	select BOARD_LATE_INIT
+	select CPU_V7A
+	select CPU_V7_HAS_NONSEC
+	select CPU_V7_HAS_VIRT
+	select SYS_FSL_DDR
+	select FSL_DDR_INTERACTIVE
+	select VENDOR_KM
+	imply SCSI
+	help
+	 Support for Hitachi-Powergrids EXPU1 service unit card.
+	 EXPU1 is a QorIQ LS1021a based service unit card used
+	 in XMC20 and FOX615 product families.
+
 config TARGET_LS1021ATSN
 	bool "Support ls1021atsn"
 	select ARCH_LS1021A

arch/arm/cpu/armv8/fsl-layerscape/Kconfig

@@ -223,7 +223,9 @@ config ARCH_LX2162A
 	select SYS_FSL_DDR_VER_50
 	select SYS_FSL_EC1
 	select SYS_FSL_EC2
-	select SYS_FSL_ERRATUM_A050106
+	select SYS_FSL_ERRATUM_A050204
+	select SYS_FSL_ERRATUM_A011334
+	select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
 	select SYS_FSL_HAS_RGMII
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_HAS_CCN508
@@ -253,7 +255,9 @@ config ARCH_LX2160A
 	select SYS_FSL_DDR_VER_50
 	select SYS_FSL_EC1
 	select SYS_FSL_EC2
-	select SYS_FSL_ERRATUM_A050106
+	select SYS_FSL_ERRATUM_A050204
+	select SYS_FSL_ERRATUM_A011334
+	select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
 	select SYS_FSL_HAS_RGMII
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_HAS_CCN508
@@ -371,8 +375,8 @@ config SYS_FSL_ERRATUM_A009008
 config SYS_FSL_ERRATUM_A009798
 	bool "Workaround for USB PHY erratum A009798"
 
-config SYS_FSL_ERRATUM_A050106
-	bool "Workaround for USB PHY erratum A050106"
+config SYS_FSL_ERRATUM_A050204
+	bool "Workaround for USB PHY erratum A050204"
 	help
 	  USB3.0 Receiver needs to enable fixed equalization
 	  for each of PHY instances in an SOC. This is similar

arch/arm/cpu/armv8/fsl-layerscape/cpu.c

@@ -1063,7 +1063,7 @@ int cpu_eth_init(struct bd_info *bis)
 	return error;
 }
 
-static inline int check_psci(void)
+int check_psci(void)
 {
 	unsigned int psci_ver;
 

arch/arm/cpu/armv8/fsl-layerscape/cpu.h

@@ -6,3 +6,4 @@
 int fsl_qoriq_core_to_cluster(unsigned int core);
 u32 initiator_type(u32 cluster, int init_id);
 u32 cpu_mask(void);
+int check_psci(void);

arch/arm/cpu/armv8/fsl-layerscape/fdt.c

@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2014-2015 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
+ * Copyright 2020-2021 NXP
  */
 
 #include <common.h>
@@ -478,6 +478,151 @@ static bool crypto_is_disabled(unsigned int svr)
 	return false;
 }
 
+#ifdef CONFIG_FSL_PFE
+void pfe_set_firmware_in_fdt(void *blob, int pfenode, void *pfw, char *pename,
+			     unsigned int len)
+{
+	int rc, fwnode;
+	unsigned int phandle;
+	char subnode_str[32], prop_str[32], phandle_str[32], s[64];
+
+	sprintf(subnode_str, "pfe-%s-firmware", pename);
+	sprintf(prop_str, "fsl,pfe-%s-firmware", pename);
+	sprintf(phandle_str, "fsl,%s-firmware", pename);
+
+	/*Add PE FW to fdt.*/
+	/* Increase the size of the fdt to make room for the node. */
+	rc = fdt_increase_size(blob, len);
+	if (rc < 0) {
+		printf("Unable to make room for %s firmware: %s\n", pename,
+		       fdt_strerror(rc));
+		return;
+	}
+
+	/* Create the firmware node. */
+	fwnode = fdt_add_subnode(blob, pfenode, subnode_str);
+	if (fwnode < 0) {
+		fdt_get_path(blob, pfenode, s, sizeof(s));
+		printf("Could not add firmware node to %s: %s\n", s,
+		       fdt_strerror(fwnode));
+		return;
+	}
+
+	rc = fdt_setprop_string(blob, fwnode, "compatible", prop_str);
+	if (rc < 0) {
+		fdt_get_path(blob, fwnode, s, sizeof(s));
+		printf("Could not add compatible property to node %s: %s\n", s,
+		       fdt_strerror(rc));
+		return;
+	}
+
+	rc = fdt_setprop_u32(blob, fwnode, "length", len);
+	if (rc < 0) {
+		fdt_get_path(blob, fwnode, s, sizeof(s));
+		printf("Could not add compatible property to node %s: %s\n", s,
+		       fdt_strerror(rc));
+		return;
+	}
+
+	/*create phandle and set the property*/
+	phandle = fdt_create_phandle(blob, fwnode);
+	if (!phandle) {
+		fdt_get_path(blob, fwnode, s, sizeof(s));
+		printf("Could not add phandle property to node %s: %s\n", s,
+		       fdt_strerror(rc));
+		return;
+	}
+
+	rc = fdt_setprop(blob, fwnode, phandle_str, pfw, len);
+	if (rc < 0) {
+		fdt_get_path(blob, fwnode, s, sizeof(s));
+		printf("Could not add firmware property to node %s: %s\n", s,
+		       fdt_strerror(rc));
+		return;
+	}
+}
+
+void fdt_fixup_pfe_firmware(void *blob)
+{
+	int pfenode;
+	unsigned int len_class = 0, len_tmu = 0, len_util = 0;
+	const char *p;
+	void *pclassfw, *ptmufw, *putilfw;
+
+	/* The first PFE we find, will contain the actual firmware. */
+	pfenode = fdt_node_offset_by_compatible(blob, -1, "fsl,pfe");
+	if (pfenode < 0)
+		/* Exit silently if there are no PFE devices */
+		return;
+
+	/* If we already have a firmware node, then also exit silently. */
+	if (fdt_node_offset_by_compatible(blob, -1,
+					  "fsl,pfe-class-firmware") > 0)
+		return;
+
+	/* If the environment variable is not set, then exit silently */
+	p = env_get("class_elf_firmware");
+	if (!p)
+		return;
+
+	pclassfw = (void *)simple_strtoul(p, NULL, 16);
+	if (!pclassfw)
+		return;
+
+	p = env_get("class_elf_size");
+	if (!p)
+		return;
+	len_class = simple_strtoul(p, NULL, 16);
+
+	/* If the environment variable is not set, then exit silently */
+	p = env_get("tmu_elf_firmware");
+	if (!p)
+		return;
+
+	ptmufw = (void *)simple_strtoul(p, NULL, 16);
+	if (!ptmufw)
+		return;
+
+	p = env_get("tmu_elf_size");
+	if (!p)
+		return;
+	len_tmu = simple_strtoul(p, NULL, 16);
+
+	if (len_class == 0 || len_tmu == 0) {
+		printf("PFE FW corrupted. CLASS FW size %d, TMU FW size %d\n",
+		       len_class, len_tmu);
+		return;
+	}
+
+	/*Add CLASS FW to fdt.*/
+	pfe_set_firmware_in_fdt(blob, pfenode, pclassfw, "class", len_class);
+
+	/*Add TMU FW to fdt.*/
+	pfe_set_firmware_in_fdt(blob, pfenode, ptmufw, "tmu", len_tmu);
+
+	/* Util PE firmware is handled separately as it is not a usual case*/
+	p = env_get("util_elf_firmware");
+	if (!p)
+		return;
+
+	putilfw = (void *)simple_strtoul(p, NULL, 16);
+	if (!putilfw)
+		return;
+
+	p = env_get("util_elf_size");
+	if (!p)
+		return;
+	len_util = simple_strtoul(p, NULL, 16);
+
+	if (len_util) {
+		printf("PFE Util PE firmware is not added to FDT.\n");
+		return;
+	}
+
+	pfe_set_firmware_in_fdt(blob, pfenode, putilfw, "util", len_util);
+}
+#endif
+
 void ft_cpu_setup(void *blob, struct bd_info *bd)
 {
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@@ -534,6 +679,9 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
 #ifdef CONFIG_SYS_DPAA_FMAN
 	fdt_fixup_fman_firmware(blob);
 #endif
+#ifdef CONFIG_FSL_PFE
+	fdt_fixup_pfe_firmware(blob);
+#endif
 #ifndef CONFIG_ARCH_LS1012A
 	fsl_fdt_disable_usb(blob);
 #endif

arch/arm/cpu/armv8/fsl-layerscape/mp.c

@@ -10,10 +10,12 @@
 #include <asm/cache.h>
 #include <asm/global_data.h>
 #include <asm/io.h>
+#include <asm/ptrace.h>
 #include <asm/system.h>
 #include <asm/arch/mp.h>
 #include <asm/arch/soc.h>
 #include <linux/delay.h>
+#include <linux/psci.h>
 #include "cpu.h"
 #include <asm/arch-fsl-layerscape/soc.h>
 #include <efi_loader.h>
@@ -301,24 +303,41 @@ int cpu_release(u32 nr, int argc, char *const argv[])
 	u64 *table = get_spin_tbl_addr();
 	int pos;
 
-	pos = core_to_pos(nr);
-	if (pos <= 0)
-		return -1;
-
-	table += pos * WORDS_PER_SPIN_TABLE_ENTRY;
 	boot_addr = simple_strtoull(argv[0], NULL, 16);
-	table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX] = boot_addr;
-	flush_dcache_range((unsigned long)table,
+
+	if (check_psci()) {
+		/* SPIN Table is used */
+		pos = core_to_pos(nr);
+		if (pos <= 0)
+			return -1;
+
+		table += pos * WORDS_PER_SPIN_TABLE_ENTRY;
+		table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX] = boot_addr;
+		flush_dcache_range((unsigned long)table,
 			   (unsigned long)table + SPIN_TABLE_ELEM_SIZE);
-	asm volatile("dsb st");
+		asm volatile("dsb st");
 
-	/*
-	 * The secondary CPUs polling the spin-table above for a non-zero
-	 * value. To save power "wfe" is called. Thus call "sev" here to
-	 * wake the CPUs and let them check the spin-table again (see
-	 * slave_cpu loop in lowlevel.S)
-	 */
-	asm volatile("sev");
+		/*
+		 * The secondary CPUs polling the spin-table above for a non-zero
+		 * value. To save power "wfe" is called. Thus call "sev" here to
+		 * wake the CPUs and let them check the spin-table again (see
+		 * slave_cpu loop in lowlevel.S)
+		 */
+		asm volatile("sev");
+	} else {
+		/* Use PSCI to kick the core */
+		struct pt_regs regs;
+
+		printf("begin to kick cpu core #%d to address %llx\n",
+		       nr, boot_addr);
+		regs.regs[0] = PSCI_0_2_FN64_CPU_ON;
+		regs.regs[1] = nr;
+		regs.regs[2] = boot_addr;
+		regs.regs[3] = 0;
+		smc_call(&regs);
+		if (regs.regs[0])
+			return -1;
+	}
 
 	return 0;
 }

arch/arm/cpu/armv8/fsl-layerscape/soc.c

@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2014-2015 Freescale Semiconductor
- * Copyright 2019-2020 NXP
+ * Copyright 2019-2021 NXP
  */
 
 #include <common.h>
@@ -218,7 +218,7 @@ static void erratum_a009007(void)
 }
 
 #if defined(CONFIG_FSL_LSCH3)
-static void erratum_a050106(void)
+static void erratum_a050204(void)
 {
 #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 	void __iomem *dcsr = (void __iomem *)DCSR_BASE;
@@ -378,7 +378,7 @@ void fsl_lsch3_early_init_f(void)
 	erratum_a009798();
 	erratum_a008997();
 	erratum_a009007();
-	erratum_a050106();
+	erratum_a050204();
 #ifdef CONFIG_CHAIN_OF_TRUST
 	/* In case of Secure Boot, the IBR configures the SMMU
 	* to allow only Secure transactions.

arch/arm/dts/Makefile

@@ -411,6 +411,7 @@ dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \
 	ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \
 	ls1021a-iot-duart.dtb ls1021a-tsn.dtb
 dtb-$(CONFIG_TARGET_PG_WCOM_SELI8) += ls1021a-pg-wcom-seli8.dtb
+dtb-$(CONFIG_TARGET_PG_WCOM_EXPU1) += ls1021a-pg-wcom-expu1.dtb
 
 dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
 	fsl-ls2080a-qds-42-x.dtb \

arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts

@@ -41,8 +41,9 @@
 
 		qca,clk-out-frequency = <125000000>;
 		qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
+		qca,keep-pll-enabled;
 
-		vddio-supply = <&vddh>;
+		vddio-supply = <&vddio>;
 
 		vddio: vddio-regulator {
 			regulator-name = "VDDIO";

arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts

@@ -32,8 +32,9 @@
 
 		qca,clk-out-frequency = <125000000>;
 		qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
+		qca,keep-pll-enabled;
 
-		vddio-supply = <&vddh>;
+		vddio-supply = <&vddio>;
 
 		vddio: vddio-regulator {
 			regulator-name = "VDDIO";

arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi

@@ -5,7 +5,7 @@
  * Some assumptions are made:
  *    * mezzanine card M8 is connected to IO SLOT1 (25g-aui for DPMAC 3,4,5,6)
  *
- * Copyright 2020 NXP
+ * Copyright 2020-2021 NXP
  *
  */
 
@@ -56,3 +56,9 @@
 		reg = <0x3>;
 	};
 };
+
+&esdhc1 {
+	mmc-hs200-1_8v;
+	mmc-hs400-1_8v;
+	bus-width = <8>;
+};