Skip to content

Commit

Permalink
Browse files Browse the repository at this point in the history
…oot-riscv

- ae350 related dts fixes.
  • Loading branch information
trini committed Jun 17, 2021
2 parents b2c4b7f + 62ce0a0 commit 7e585b5
Show file tree
Hide file tree
Showing 5 changed files with 68 additions and 23 deletions.
52 changes: 52 additions & 0 deletions arch/riscv/dts/ae350-u-boot.dtsi
Original file line number Diff line number Diff line change
@@ -0,0 +1,52 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)

/ {
cpus {
u-boot,dm-spl;
CPU0: cpu@0 {
u-boot,dm-spl;
CPU0_intc: interrupt-controller {
u-boot,dm-spl;
};
};
CPU1: cpu@1 {
u-boot,dm-spl;
CPU1_intc: interrupt-controller {
u-boot,dm-spl;
};
};
CPU2: cpu@2 {
u-boot,dm-spl;
CPU2_intc: interrupt-controller {
u-boot,dm-spl;
};
};
CPU3: cpu@3 {
u-boot,dm-spl;
CPU3_intc: interrupt-controller {
u-boot,dm-spl;
};
};
};

memory@0 {
u-boot,dm-spl;
};

soc {
u-boot,dm-spl;

plic1: interrupt-controller@e6400000 {
u-boot,dm-spl;
};

plmt0@e6000000 {
u-boot,dm-spl;
};
};

serial0: serial@f0300000 {
u-boot,dm-spl;
};

};
9 changes: 5 additions & 4 deletions arch/riscv/dts/ae350_32.dts
Original file line number Diff line number Diff line change
@@ -1,6 +1,9 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)

/dts-v1/;

#include "binman.dtsi"
#include "ae350-u-boot.dtsi"

/ {
#address-cells = <1>;
Expand All @@ -14,7 +17,7 @@
};

chosen {
bootargs = "console=ttyS0,38400n8 debug loglevel=7";
bootargs = "console=ttyS0,38400n8 debug loglevel=7";
stdout-path = "uart0:38400n8";
};

Expand Down Expand Up @@ -133,8 +136,7 @@

plic0: interrupt-controller@e4000000 {
compatible = "riscv,plic0";
#address-cells = <1>;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
interrupt-controller;
reg = <0xe4000000 0x2000000>;
riscv,ndev=<71>;
Expand All @@ -146,7 +148,6 @@

plic1: interrupt-controller@e6400000 {
compatible = "riscv,plic1";
#address-cells = <1>;
#interrupt-cells = <1>;
interrupt-controller;
reg = <0xe6400000 0x400000>;
Expand Down
7 changes: 4 additions & 3 deletions arch/riscv/dts/ae350_64.dts
Original file line number Diff line number Diff line change
@@ -1,6 +1,9 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)

/dts-v1/;

#include "binman.dtsi"
#include "ae350-u-boot.dtsi"

/ {
#address-cells = <2>;
Expand All @@ -14,7 +17,7 @@
};

chosen {
bootargs = "console=ttyS0,38400n8 debug loglevel=7";
bootargs = "console=ttyS0,38400n8 debug loglevel=7";
stdout-path = "uart0:38400n8";
};

Expand Down Expand Up @@ -133,7 +136,6 @@

plic0: interrupt-controller@e4000000 {
compatible = "riscv,plic0";
#address-cells = <2>;
#interrupt-cells = <2>;
interrupt-controller;
reg = <0x0 0xe4000000 0x0 0x2000000>;
Expand All @@ -146,7 +148,6 @@

plic1: interrupt-controller@e6400000 {
compatible = "riscv,plic1";
#address-cells = <2>;
#interrupt-cells = <2>;
interrupt-controller;
reg = <0x0 0xe6400000 0x0 0x400000>;
Expand Down
4 changes: 3 additions & 1 deletion arch/riscv/lib/andes_plic.c
Original file line number Diff line number Diff line change
Expand Up @@ -105,9 +105,11 @@ int riscv_clear_ipi(int hart)

int riscv_get_ipi(int hart, int *pending)
{
unsigned int ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));

*pending = readl((void __iomem *)PENDING_REG(gd->arch.plic,
gd->arch.boot_hart));
*pending = !!(*pending & SEND_IPI_TO_HART(hart));
*pending = !!(*pending & ipi);

return 0;
}
Expand Down
19 changes: 4 additions & 15 deletions doc/board/AndesTech/ax25-ae350.rst
Original file line number Diff line number Diff line change
Expand Up @@ -58,15 +58,6 @@ Platform Level Interrupt Controller (PLIC)
- Configurable number of targets: 1-16
- Preempted interrupt priority stack

Configurations
--------------

CONFIG_SKIP_LOWLEVEL_INIT:

If you want to boot this system from SPI ROM and bypass e-bios (the
other boot loader on ROM). You should undefine CONFIG_SKIP_LOWLEVEL_INIT
in "include/configs/ax25-ae350.h".

Build and boot steps
--------------------

Expand All @@ -89,12 +80,10 @@ Verification:
Steps
-----

1. Define CONFIG_SKIP_LOWLEVEL_INIT to build u-boot which is loaded via gdb from ram.
2. Undefine CONFIG_SKIP_LOWLEVEL_INIT to build u-boot which is booted from spi rom.
3. Ping a server by mac driver
4. Scan sd card and copy u-boot image which is booted from flash to ram by sd driver.
5. Burn this u-boot image to spi rom by spi driver
6. Re-boot u-boot from spi flash with power off and power on.
1. Ping a server by mac driver
2. Scan sd card and copy u-boot image which is booted from flash to ram by sd driver
3. Burn this u-boot image to spi rom by spi driver
4. Re-boot u-boot from spi flash with power off and power on

Messages of U-Boot boot on AE350 board
--------------------------------------
Expand Down

0 comments on commit 7e585b5

Please sign in to comment.