This design includes changed PLIC component which includes 1 additional timer block located @D000000 and connected to interrupt source 15 (interrupt number 16 from firmware perspective).
FPGA BIT file: shiri-timer-R1.zip
Reference firmware:
fw-fpga-shiri-block-at-D00.zip
Reference firmware source:
https://github.com/daynix/opensbi/tree/shiri