Shiri's release with timer block at 0xD000000

This design includes changed PLIC component which includes 1 additional timer block located @D000000 and connected to interrupt source 15 (interrupt number 16 from firmware perspective).
FPGA BIT file: shiri-timer-R1.zip
Reference firmware:
fw-fpga-shiri-block-at-D00.zip
Reference firmware source:
https://github.com/daynix/opensbi/tree/shiri

Yuri's fallback with 2 additional APB timers

This drop includes a quick/simple change in the mainstream CVA6 design by changing existing define to instantiate 4 APB times (2 timers in the original design). All the APB timer are located in the MMIO area 0x18000000. There are 16 bytes allocated for each APB timer, each APB timer is able to raise 2 interrupts (first for for wrap-around, second one for match between current counter and programmed counter). In firmware perspective for APB0 this is interrupts 4 and 5, for APB1 - interrupts 6 and 7, for APB2 - 8 and 9, for APB3 - 10 and 11. Wrap-around interrupts is not used, the reference firmware uses APB3 timer as the trigger to a periodic machine-mode code execution.
FPGA BIT file: apb-4-timers.zip
Reference firmware: https://github.com/daynix/opensbi/tree/apb3-liran