Fix overwriting typedef name when processing packed enum #6053

Job	Run time
Build tools	11m 2s
Build Synlig Release	4m 55s
Build Plugin	4m 33s
Build Synlig (ASAN)	8m 36s
Emit Workflow Info	0s
Build Package	5m 22s
Build PySynlig	10m 30s
Style check	1m 25s
Verify README Correctness (Installation From Sources)	43m 7s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs	7m 23s
Parsing Tests / Test read_systemverilog release	4m 49s
Large Designs Tests / Ibex (Vivado synthesis)	8m 39s
Parsing Tests / Test read_uhdm release	4m 15s
Large Designs Tests / Ibex (F4PGA synthesis)	11m 5s
Large Designs Tests / Opentitan (synthesis)	1h 3m 47s
Parsing Tests / Test read_systemverilog plugin	5m 58s
Parsing Tests / Test read_uhdm plugin	6m 9s
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)	16m 29s
Parsing Tests / Test read_systemverilog asan	36m 43s
Large Designs Tests / Opentitan 9d82960888 (synthesis)	33m 8s
Parsing Tests / Test read_uhdm asan	25m 40s
Large Designs Tests / Opentitan parsing (full/top-down)	12m 11s
Large Designs Tests / Opentitan parsing (quick)	5m 35s
Large Designs Tests / VeeR-EH1 (synthesis)	5m 6s
Large Designs Tests / Black Parrot (ASIC synthesis)	41m 18s
Large Designs Tests / Black Parrot (AMD (Xilinx) with PySynlig)	39m 49s
Formal Verification Tests / simple	17m 45s
Formal Verification Tests / sv2v	16m 53s
Formal Verification Tests / yosys	14m 19s
Parsing Tests / Summary Generation	1m 27s
Parsing Tests / Generate AST diff	2m 24s
Release Package	0s
Verify README Correctness (Download And Run Release)	0s
	7h 50m 22s

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