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fix(bank_conflict): fix oldest selection logic #4039

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fix(bank_conflict): fix oldest selection logic #4039

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4 changes: 2 additions & 2 deletions src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -419,7 +419,7 @@ class SramedDataArray(implicit p: Parameters) extends AbstractBankedDataArray {
val load_req_index = (0 until LoadPipelineWidth).map(_.asUInt)


val load_req_bank_conflict_selcet = selcetOldestPort(load_req_valid, load_req_lqIdx, load_req_index)
val load_req_bank_conflict_selcet = selcetOldestPort(load_req_with_bank_conflict, load_req_lqIdx, load_req_index)
val load_req_bank_select_port = UIntToOH(load_req_bank_conflict_selcet._2).asBools

val rr_bank_conflict_oldest = (0 until LoadPipelineWidth).map(i =>
Expand Down Expand Up @@ -698,7 +698,7 @@ class BankedDataArray(implicit p: Parameters) extends AbstractBankedDataArray {
val load_req_lqIdx = io.read.map(_.bits.lqIdx)
val load_req_index = (0 until LoadPipelineWidth).map(_.asUInt)

val load_req_bank_conflict_selcet = selcetOldestPort(load_req_valid, load_req_lqIdx, load_req_index)
val load_req_bank_conflict_selcet = selcetOldestPort(load_req_with_bank_conflict, load_req_lqIdx, load_req_index)
val load_req_bank_select_port = UIntToOH(load_req_bank_conflict_selcet._2).asBools

val rr_bank_conflict_oldest = (0 until LoadPipelineWidth).map(i =>
Expand Down
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