submodule(utility), transforms: collect XSLogs to SimTop.LogPerfEndpoint

src/main/scala/device/AXI4SlaveModule.scala

@@ -62,27 +62,25 @@ class AXI4SlaveModuleImp[T<:Data](outer: AXI4SlaveModule[T])
 
 
 //  val timer = GTimer()
-  when(in.ar.fire){
-    XSDebug(p"[ar] addr: ${Hexadecimal(in.ar.bits.addr)} " +
-      p"arlen:${in.ar.bits.len} arsize:${in.ar.bits.size} " +
-      p"id: ${in.ar.bits.id}\n"
-    )
-  }
-  when(in.aw.fire){
-    XSDebug(p"[aw] addr: ${Hexadecimal(in.aw.bits.addr)} " +
-      p"awlen:${in.aw.bits.len} awsize:${in.aw.bits.size} " +
-      p"id: ${in.aw.bits.id}\n"
-    )
-  }
-  when(in.w.fire){
-    XSDebug(p"[w] wmask: ${Binary(in.w.bits.strb)} last:${in.w.bits.last} data:${Hexadecimal(in.w.bits.data)}\n")
-  }
-  when(in.b.fire){
-    XSDebug(p"[b] id: ${in.b.bits.id}\n")
-  }
-  when(in.r.fire){
-    XSDebug(p"[r] id: ${in.r.bits.id} data: ${Hexadecimal(in.r.bits.data)}\n")
-  }
+  XSDebug(in.ar.fire,
+    p"[ar] addr: ${Hexadecimal(in.ar.bits.addr)} " +
+    p"arlen:${in.ar.bits.len} arsize:${in.ar.bits.size} " +
+    p"id: ${in.ar.bits.id}\n"
+  )
+  XSDebug(in.aw.fire,
+    p"[aw] addr: ${Hexadecimal(in.aw.bits.addr)} " +
+    p"awlen:${in.aw.bits.len} awsize:${in.aw.bits.size} " +
+    p"id: ${in.aw.bits.id}\n"
+  )
+  XSDebug(in.w.fire,
+    p"[w] wmask: ${Binary(in.w.bits.strb)} last:${in.w.bits.last} data:${Hexadecimal(in.w.bits.data)}\n"
+  )
+  XSDebug(in.b.fire,
+    p"[b] id: ${in.b.bits.id}\n"
+  )
+  XSDebug(in.r.fire,
+    p"[r] id: ${in.r.bits.id} data: ${Hexadecimal(in.r.bits.data)}\n"
+  )
 
   when(in.aw.fire){
     assert(in.aw.bits.burst === AXI4Parameters.BURST_INCR, "only support busrt ince!")

src/main/scala/device/TLTimer.scala

@@ -65,10 +65,8 @@ class TLTimer(address: Seq[AddressSet], sim: Boolean, numCores: Int)(implicit p:
     node.regmap( mapping = clintMapping:_* )
 
     val in = node.in.head._1
-    when(in.a.valid){
-      XSDebug("[A] channel valid ready=%d ", in.a.ready)
-      in.a.bits.dump
-    }
+    XSDebug(in.a.valid, "[A] channel valid ready=%d ", in.a.ready)
+    in.a.bits.dump(in.a.valid)
 
     for (i <- 0 until numCores) {
       io.mtip(i) := RegNext(mtime >= mtimecmp(i))

src/main/scala/utils/DebugIdentityNode.scala

@@ -40,12 +40,10 @@ class DebugIdentityNode()(implicit p: Parameters) extends LazyModule  {
     def debug(t: TLBundle, valid: Boolean = false): Unit ={
       def fire[T <: Data](x: DecoupledIO[T]) = if(valid) x.valid else x.fire
       val channels = Seq(t.a, t.b, t.c, t.d, t.e)
-      channels.foreach(c =>
-        when(fire(c)){
-          XSDebug(" isFire:%d ",c.fire)
-          c.bits.dump
-        }
-      )
+      channels.foreach { c =>
+        XSDebug(fire(c), " isFire:%d ", c.fire)
+        c.bits.dump(fire(c))
+      }
     }
     debug(in, false)
   }