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build: pass CIRCTTargetAnnotation through CHISEL_TARGET #3974

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merged 1 commit into from
Dec 3, 2024
Merged

build: pass CIRCTTargetAnnotation through CHISEL_TARGET #3974

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4 changes: 4 additions & 0 deletions .github/workflows/emu.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -74,6 +74,10 @@ jobs:
run: |
python3 $GITHUB_WORKSPACE/.github/workflows/check_verilog.py build/rtl
python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --clean
- name: generate chirrtl only
run: |
make sim-verilog CHISEL_TARGET=chirrtl
python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --clean
- name: build MinimalConfig Release emu
run: |
python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --build \
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7 changes: 6 additions & 1 deletion Makefile
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Expand Up @@ -37,6 +37,7 @@ MEM_GEN_SEP = ./scripts/gen_sep_mem.sh
CONFIG ?= DefaultConfig
NUM_CORES ?= 1
ISSUE ?= E.b
CHISEL_TARGET ?= systemverilog

SUPPORT_CHI_ISSUE = B E.b
ifeq ($(findstring $(ISSUE), $(SUPPORT_CHI_ISSUE)),)
Expand All @@ -56,7 +57,7 @@ endif
# common chisel args
FPGA_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(TOP).$(RTL_SUFFIX).conf"
SIM_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(SIM_TOP).$(RTL_SUFFIX).conf"
MFC_ARGS = --dump-fir --target systemverilog --split-verilog \
MFC_ARGS = --dump-fir --target $(CHISEL_TARGET) --split-verilog \
--firtool-opt "-O=release --disable-annotation-unknown --lowering-options=explicitBitcast,disallowLocalVariables,disallowPortDeclSharing,locationInfoStyle=none"
RELEASE_ARGS += $(MFC_ARGS)
DEBUG_ARGS += $(MFC_ARGS)
Expand Down Expand Up @@ -151,6 +152,7 @@ $(TOP_V): $(SCALA_FILE)
$(TIME_CMD) mill -i xiangshan.runMain $(FPGATOP) \
--target-dir $(@D) --config $(CONFIG) --issue $(ISSUE) $(FPGA_MEM_ARGS) \
--num-cores $(NUM_CORES) $(RELEASE_ARGS)
ifeq ($(CHISEL_TARGET),systemverilog)
$(MEM_GEN_SEP) "$(MEM_GEN)" "[email protected]" "$(@D)"
@git log -n 1 >> .__head__
@git diff >> .__diff__
Expand All @@ -159,6 +161,7 @@ $(TOP_V): $(SCALA_FILE)
@cat .__head__ .__diff__ $@ > .__out__
@mv .__out__ $@
@rm .__head__ .__diff__
endif

verilog: $(TOP_V)

Expand All @@ -169,6 +172,7 @@ $(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE)
$(TIME_CMD) mill -i xiangshan.test.runMain $(SIMTOP) \
--target-dir $(@D) --config $(CONFIG) --issue $(ISSUE) $(SIM_MEM_ARGS) \
--num-cores $(NUM_CORES) $(SIM_ARGS) --full-stacktrace
ifeq ($(CHISEL_TARGET),systemverilog)
$(MEM_GEN_SEP) "$(MEM_GEN)" "[email protected]" "$(@D)"
@git log -n 1 >> .__head__
@git diff >> .__diff__
Expand All @@ -188,6 +192,7 @@ else
endif
endif
sed -i -e "s/\$$error(/\$$fwrite(32\'h80000002, /g" $(RTL_DIR)/*.$(RTL_SUFFIX)
endif

sim-verilog: $(SIM_TOP_V)

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