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feat(Backend, MemBlock): add support for Zacas extension #3958

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merged 7 commits into from
Dec 10, 2024
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@linjuanZ linjuanZ commented Nov 29, 2024

This pull request implements Zacas extension for atomic Compare-and-Swap (CAS) instructions. For RV64, AMOCAS.W / AMOCAS.D / AMOCAS.Q atomically loads 32 / 64 / 128-bits of a data value from rs1, compares the loaded value to register rd (for AMOCAS.Q, a register pair consisting of rd and rd+1), and if the comparison is bitwise equal, then stores the value held in rs2 (for AMOCAS.Q, a register pair consisting of rs2 and rs2+1) to the original address in rs1.

This pull request re-uses the existing AtomicsUnit design. However, an AMOCAS instruction may consume more than 1 std and even more than 1 sta in the new design. As far as stds,

  • for AMOs (except AMOCAS) and LR/SC, 1 std uop is wanted: X(rs2) with uopIdx = 0
  • for AMOCAS.W / AMOCAS.D, 2 std uops are wanted: X(rd), X(rs2) with uopIdx = 0, 1
  • for AMOCAS.Q, 4 std uops are wanted: X(rd), X(rs2), X(rd+1), X(rs2+1) with uopIdx = 0, 1, 2, 3

As for stas, AMOCAS.Q has extra require for the number of sta uops, which is also the number of sta uops' write-back,

  • for AMOs (except AMOCAS.Q) and LR/SC, 1 sta uop is wanted: X(rs1) with uopIdx = 0
  • for AMOCAS.Q, 2 sta uops are wanted: X(rs1)*2 with uopIdx = 0, 2

Besides, this pr removes the write-back of atomic stds.

@linjuanZ linjuanZ force-pushed the feat-zacas branch 2 times, most recently from f73e10d to f19d2a9 Compare December 6, 2024 02:34
@NewPaulWalker NewPaulWalker force-pushed the feat-zacas branch 3 times, most recently from 2dd4a60 to 907f8cc Compare December 9, 2024 03:41
@linjuanZ linjuanZ marked this pull request as ready for review December 9, 2024 08:35
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DCache part LGTM.

NewPaulWalker and others added 3 commits December 9, 2024 19:48
misc: remove assert temporarily
fix(AtomicsUnit, MemBlock): fix loss of multiple stds

In the previous design, AtomicsUnit receives stds from StdExeUnit and
arbitrate at most one std uop for one cycle. This works fine on most of
the AMOs and LR/SC because they require only one std uop. However AMOCAS
requires at least two std uops, which may be issued from two separate
issue queues at the same time, leading to the loss of std uops.

This commit fixes this by taking all the outputs of the StdExeUnits into
account with arbitration logics.

fix(AtomicsUnit): DCache req can only be sent at `s_cache_req`

fix(AtomicsUnit, difftest): fix difftest io for atomic events

fix(MainPipe): fix precedence of `&` and `=/=` operator

fix(MainPipe): AMOCAS should not wait for AMOALU

fix(MemBlock): remove unnecessary assertion

fix(MainPipe): only CAS instruction can assert `s3_cas_fail`

fix(AtomicsUnit): fix bug in data select logic

submodule(difftest): bump difftest
NewPaulWalker and others added 4 commits December 9, 2024 19:49
* spike commit: 9ab4cebc0caf121695b77f78ca6d2481fe9b182f
* spike config: CPU=XIANGSHAN

Including:
    * feat(Zacas): enable Zacas entension.

* NEMU commit: bf877e0b34092517c909afc9c58ebc803dd8cf3f
* NEMU configs:
    * riscv64-xs-ref_defconfig
    * riscv64-dual-xs-ref_defconfig

Including:
    * config(Zacas): enable Zacas entension.
    * submodule(ready-to-run): Bump spike ref in ready-to-run
    * ci: add ci tests for Zacas extension.
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[Generated by IPC robot]
commit: 3f5c2cb

commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
3f5c2cb 1.959 0.450 2.686 1.230 2.832 2.461 2.393 0.919 1.407 1.992 3.434 2.704 2.383 3.261

master branch:

commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
ad15bdb
fad7803
df65a16
7d20eb3 1.959 0.450 2.686 1.226 2.832 2.461 2.393 0.919 1.407 1.992 3.435 2.709 2.383 3.261
35477a7

@linjuanZ linjuanZ merged commit 287a3ff into master Dec 10, 2024
9 checks passed
@linjuanZ linjuanZ deleted the feat-zacas branch December 10, 2024 00:49
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5 participants