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feat(DCache RAS): add DCache RAS inject support
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
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| /*************************************************************************************** | ||
| * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences | ||
| * Copyright (c) 2020-2021 Peng Cheng Laboratory | ||
| * | ||
| * XiangShan is licensed under Mulan PSL v2. | ||
| * You can use this software according to the terms and conditions of the Mulan PSL v2. | ||
| * You may obtain a copy of Mulan PSL v2 at: | ||
| * http://license.coscl.org.cn/MulanPSL2 | ||
| * | ||
| * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, | ||
| * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, | ||
| * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. | ||
| * | ||
| * See the Mulan PSL v2 for more details. | ||
| ***************************************************************************************/ | ||
|
|
||
| package xiangshan.cache | ||
|
|
||
| import org.chipsalliance.cde.config.Parameters | ||
| import chisel3._ | ||
| import chisel3.util._ | ||
| import freechips.rocketchip.subsystem._ | ||
| import freechips.rocketchip.diplomacy._ | ||
| import freechips.rocketchip.regmapper._ | ||
| import freechips.rocketchip.tilelink._ | ||
| import freechips.rocketchip.interrupts._ | ||
| import freechips.rocketchip.util._ | ||
| import freechips.rocketchip.util.property | ||
| import chisel3.experimental.SourceInfo | ||
| import xiangshan._ | ||
|
|
||
| case class L1CacheCtrlParams ( | ||
| address: AddressSet, | ||
| beatBytes: Int = 8, | ||
| ) { | ||
| def maxBanks = 1 | ||
| def bankBytes = 128 | ||
|
|
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| def regWidth = 64 | ||
| def regBytes = regWidth / 8 | ||
|
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| def ctrlOffset = 0x0 | ||
| def delayOffset = ctrlOffset + regBytes | ||
| def maskOffset = delayOffset + regBytes | ||
|
|
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| def nSignalComps = 2 | ||
| } | ||
|
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| class CtrlUnitCtrlBundle(implicit p: Parameters) extends XSBundle with HasDCacheParameters { | ||
| val zero0 = UInt((60-DCacheBanks).W) // padding bits | ||
| val comp = UInt(2.W) // components: 2'b01 tag, 2'b10 data | ||
| val ede = Bool() // error delay enable | ||
| val ese = Bool() // error signaling enable | ||
| } | ||
|
|
||
| class CtrlUnit(params: L1CacheCtrlParams)(implicit p: Parameters) extends LazyModule | ||
| with HasDCacheParameters | ||
| { | ||
| val device: SimpleDevice = new SimpleDevice("L1DCacheCtrl", Seq("xiangshan,l1dcache_ctrl")) | ||
|
|
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| val node: TLRegisterNode = TLRegisterNode( | ||
| address = Seq(params.address), | ||
| device = device, | ||
| beatBytes = params.beatBytes, | ||
| concurrency = 1, | ||
| ) | ||
|
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| lazy val module = new CtrlUnitImp | ||
|
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| class CtrlUnitImp extends LazyModuleImp(this) { | ||
| val io_pseudoError = IO(Vec(params.nSignalComps, DecoupledIO(Vec(DCacheBanks, UInt(DCacheSRAMRowBits.W))))) | ||
|
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| require(params.maxBanks > 0, "At least one bank!") | ||
| require(params.maxBanks == 1, "Is it necessary to have more than 1 bank?") | ||
| require(params.regWidth == DCacheSRAMRowBits, "regWidth must be equal to DCacheSRAMRowBits!") | ||
| val ctrlRegs = RegInit(VecInit(Seq.fill(1)(0.U(params.regWidth.W)))) | ||
| val delayRegs = RegInit(VecInit(Seq.fill(1)(0.U(params.regWidth.W)))) | ||
| val maskRegs = RegInit(VecInit(Seq.fill(DCacheBanks)(0.U(DCacheSRAMRowBits.W)))) | ||
|
|
||
| io_pseudoError.zipWithIndex.foreach { | ||
| case (pErr, i) => | ||
| val ctrlReg = ctrlRegs(0) | ||
| val ctrlRegBundle = ctrlRegs(0).asTypeOf(new CtrlUnitCtrlBundle) | ||
| val delayReg = delayRegs(0) | ||
|
|
||
| require(io_pseudoError.length == ctrlRegBundle.comp.getWidth, "io_pseudoError must equal number of components!") | ||
| pErr.valid := ctrlRegBundle.ese && ctrlRegBundle.comp(i) && (!ctrlRegBundle.ede || delayReg === 0.U) | ||
| pErr.bits := maskRegs | ||
|
|
||
| when (pErr.fire) { | ||
| val newCtrlReg = WireInit(0.U.asTypeOf(ctrlRegBundle)) | ||
| newCtrlReg := ctrlRegBundle | ||
| newCtrlReg.ese := false.B | ||
|
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| ctrlReg := newCtrlReg.asUInt | ||
| } | ||
| } | ||
|
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| ctrlRegs.map(_.asTypeOf(new CtrlUnitCtrlBundle)).zip(delayRegs).foreach { | ||
| case (ctl, delay) => | ||
| when (ctl.ese && ctl.ede && delay =/= 0.U) { | ||
| delay := delay - 1.U | ||
| } | ||
| } | ||
|
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||
| def ctrlRegDesc(i: Int) = | ||
| RegFieldDesc( | ||
| name = s"control_$i", | ||
| desc = s"Acting control of controller $i", | ||
| group = Some(s"controll_${i}"), | ||
| groupDesc = Some(s"Acting control of controller ${i}"), | ||
| reset = Some(0) | ||
| ) | ||
|
|
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| def delayRegDesc(i: Int) = | ||
| RegFieldDesc( | ||
| name = s"delay_$i", | ||
| desc = s"pseudo error delay $i", | ||
| group = Some(s"delay_${i}"), | ||
| groupDesc = Some(s"pseudo error delay ${i}"), | ||
| reset = Some(0) | ||
| ) | ||
|
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| def maskRegDesc(i: Int) = | ||
| RegFieldDesc( | ||
| name = s"mask_$i", | ||
| desc = s"pseudo error toggle mask$i", | ||
| group = Some(s"mask_${i}"), | ||
| groupDesc = Some(s"pseudo error toggle mask ${i}"), | ||
| reset = Some(0) | ||
| ) | ||
|
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| def ctrlRegField(x: UInt, i: Int) = { | ||
| RegField(params.regWidth, x, ctrlRegDesc(i)) | ||
| } | ||
|
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| def delayRegField(x: UInt, i: Int) = { | ||
| RegField(params.regWidth, x, delayRegDesc(i)) | ||
| } | ||
|
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| def maskRegField(x: UInt, i: Int) = { | ||
| RegField(params.regWidth, x, maskRegDesc(i)) | ||
| } | ||
|
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| val ctrlRegFields = ctrlRegs.zipWithIndex.map { | ||
| case (reg, i) => | ||
| params.ctrlOffset -> Seq(ctrlRegField(reg, i)) | ||
| } | ||
| val delayRegFields = delayRegs.zipWithIndex.map { | ||
| case (reg, i) => | ||
| params.delayOffset -> Seq(delayRegField(reg, i)) | ||
| } | ||
| val maskRegFields = maskRegs.zipWithIndex.map { | ||
| case (reg, i) => | ||
| (params.maskOffset + 8 * i) -> Seq(maskRegField(reg, i)) | ||
| } | ||
|
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| node.regmap((ctrlRegFields ++ delayRegFields ++ maskRegFields):_*) | ||
| } | ||
| } |
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