fix(csr, imsic): sync CSR access imsic (#3989)

OpenXiangShan · Dec 9, 2024 · df65a16 · df65a16
1 parent 7d20eb3
commit df65a16
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala b/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
@@ -1231,7 +1231,7 @@ class NewCSR(implicit val p: Parameters) extends Module
   io.status.instrAddrTransType.sv48x4 := privState.isVirtual && vsatp.regOut.MODE === SatpMode.Bare && hgatp.regOut.MODE === HgatpMode.Sv48x4
   assert(PopCount(io.status.instrAddrTransType.asUInt) === 1.U, "Exactly one inst trans type should be asserted")
 
-  private val csrAccess = wenLegal || ren
+  private val csrAccess = wenLegalReg || RegNext(ren)
 
   private val imsicAddrValid =
     csrAccess &&  addr === CSRs.mireg.U &&  miselect.inIMSICRange ||