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refactor(Frontend): add ExceptionType.hasExcaption wrapper (#3866)
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#3787 (comment)
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@ngc7331
ngc7331 authored Nov 14, 2024
1 parent a751b11 commit dd02bc3
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Showing 4 changed files with 17 additions and 15 deletions.
4 changes: 3 additions & 1 deletion src/main/scala/xiangshan/frontend/FrontendBundle.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -114,7 +114,9 @@ object ExceptionType {
def af: UInt = "b11".U // instruction access fault
def width: Int = 2

def hasException(e: UInt): Bool = e =/= none
def hasException(e: UInt): Bool = e =/= none
def hasException(e: Vec[UInt]): Bool = e.map(_ =/= none).reduce(_ || _)
def hasException(e: IndexedSeq[UInt]): Bool = hasException(VecInit(e))

def fromOH(has_pf: Bool, has_gpf: Bool, has_af: Bool): UInt = {
assert(
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12 changes: 6 additions & 6 deletions src/main/scala/xiangshan/frontend/IFU.scala
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Expand Up @@ -395,7 +395,7 @@ class NewIFU(implicit p: Parameters) extends XSModule

// FIXME: what if port 0 is not mmio, but port 1 is?
// cancel mmio fetch if exception occurs
val f2_mmio = f2_exception(0) === ExceptionType.none && (
val f2_mmio = !ExceptionType.hasException(f2_exception(0)) && (
fromICache(0).bits.pmp_mmio ||
// currently, we do not distinguish between Pbmt.nc and Pbmt.io
// anyway, they are both non-cacheable, and should be handled with mmio fsm and sent to Uncache module
Expand Down Expand Up @@ -486,7 +486,7 @@ class NewIFU(implicit p: Parameters) extends XSModule
*/
val f2_crossPage_exception_vec = VecInit((0 until PredictWidth).map { i =>
Mux(
isLastInLine(f2_pc(i)) && !f2_pd(i).isRVC && f2_doubleLine && f2_exception(0) === ExceptionType.none,
isLastInLine(f2_pc(i)) && !f2_pd(i).isRVC && f2_doubleLine && !ExceptionType.hasException(f2_exception(0)),
f2_exception(1),
ExceptionType.none
)
Expand Down Expand Up @@ -706,7 +706,7 @@ class NewIFU(implicit p: Parameters) extends XSModule
assert(!io.iTLBInter.resp.bits.miss, "blocked mode iTLB miss when resp.fire")
val tlb_exception = ExceptionType.fromTlbResp(io.iTLBInter.resp.bits)
// if tlb has exception, abort checking pmp, just send instr & exception to ibuffer and wait for commit
mmio_state := Mux(tlb_exception === ExceptionType.none, m_sendPMP, m_waitCommit)
mmio_state := Mux(ExceptionType.hasException(tlb_exception), m_waitCommit, m_sendPMP)
// also save itlb response
mmio_resend_addr := io.iTLBInter.resp.bits.paddr(0)
mmio_resend_exception := tlb_exception
Expand All @@ -719,7 +719,7 @@ class NewIFU(implicit p: Parameters) extends XSModule
// if pmp re-check does not respond mmio, must be access fault
val pmp_exception = Mux(io.pmp.resp.mmio, ExceptionType.fromPMPResp(io.pmp.resp), ExceptionType.af)
// if pmp has exception, abort sending request, just send instr & exception to ibuffer and wait for commit
mmio_state := Mux(pmp_exception === ExceptionType.none, m_resendReq, m_waitCommit)
mmio_state := Mux(ExceptionType.hasException(pmp_exception), m_waitCommit, m_resendReq)
// also save pmp response
mmio_resend_exception := pmp_exception
}
Expand Down Expand Up @@ -871,7 +871,7 @@ class NewIFU(implicit p: Parameters) extends XSModule
case 0 => f3_backendException
case _ => false.B
}
io.toIbuffer.bits.crossPageIPFFix := f3_crossPage_exception_vec.map(_ =/= ExceptionType.none)
io.toIbuffer.bits.crossPageIPFFix := f3_crossPage_exception_vec.map(ExceptionType.hasException)
io.toIbuffer.bits.illegalInstr := f3_ill
io.toIbuffer.bits.triggered := f3_triggered

Expand Down Expand Up @@ -942,7 +942,7 @@ class NewIFU(implicit p: Parameters) extends XSModule
io.toIbuffer.bits.pd(0).isRet := isRet

io.toIbuffer.bits.exceptionType(0) := mmio_resend_exception
io.toIbuffer.bits.crossPageIPFFix(0) := mmio_resend_exception =/= ExceptionType.none
io.toIbuffer.bits.crossPageIPFFix(0) := ExceptionType.hasException(mmio_resend_exception)
io.toIbuffer.bits.illegalInstr(0) := mmioRVCExpander.io.ill

io.toIbuffer.bits.enqEnable := f3_mmio_range.asUInt
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12 changes: 6 additions & 6 deletions src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
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Expand Up @@ -268,7 +268,7 @@ class ICacheMainPipe(implicit p: Parameters) extends ICacheModule {
*/
toPMP.zipWithIndex.foreach { case (p, i) =>
// if itlb has exception, paddr can be invalid, therefore pmp check can be skipped
p.valid := s1_valid // && s1_itlb_exception === ExceptionType.none
p.valid := s1_valid // && !ExceptionType.hasException(s1_itlb_exception(i))
p.bits.addr := s1_req_paddr(i)
p.bits.size := 3.U // TODO
p.bits.cmd := TlbCmd.exec
Expand Down Expand Up @@ -442,7 +442,7 @@ class ICacheMainPipe(implicit p: Parameters) extends ICacheModule {
*/
val s2_miss = VecInit((0 until PortNumber).map { i =>
!s2_hits(i) && (if (i == 0) true.B else s2_doubleline) &&
s2_exception.take(i + 1).map(_ === ExceptionType.none).reduce(_ && _) &&
!ExceptionType.hasException(s2_exception.take(i + 1)) &&
s2_mmio.take(i + 1).map(!_).reduce(_ && _)
})

Expand Down Expand Up @@ -537,11 +537,11 @@ class ICacheMainPipe(implicit p: Parameters) extends ICacheModule {
io.perfInfo.hit_0_miss_1 := s2_hits(0) && !s2_hits(1) && s2_doubleline
io.perfInfo.miss_0_hit_1 := !s2_hits(0) && s2_hits(1) && s2_doubleline
io.perfInfo.miss_0_miss_1 := !s2_hits(0) && !s2_hits(1) && s2_doubleline
io.perfInfo.hit_0_except_1 := s2_hits(0) && (s2_exception(1) =/= ExceptionType.none) && s2_doubleline
io.perfInfo.miss_0_except_1 := !s2_hits(0) && (s2_exception(1) =/= ExceptionType.none) && s2_doubleline
io.perfInfo.hit_0_except_1 := s2_hits(0) && (ExceptionType.hasException(s2_exception(1))) && s2_doubleline
io.perfInfo.miss_0_except_1 := !s2_hits(0) && (ExceptionType.hasException(s2_exception(1))) && s2_doubleline
io.perfInfo.bank_hit(0) := s2_hits(0)
io.perfInfo.bank_hit(1) := s2_hits(1) && s2_doubleline
io.perfInfo.except_0 := s2_exception(0) =/= ExceptionType.none
io.perfInfo.except_0 := ExceptionType.hasException(s2_exception(0))
io.perfInfo.hit := s2_hits(0) && (!s2_doubleline || s2_hits(1))

/** <PERF> fetch bubble generated by icache miss */
Expand Down Expand Up @@ -581,7 +581,7 @@ class ICacheMainPipe(implicit p: Parameters) extends ICacheModule {
*/
if (env.EnableDifftest) {
val discards = (0 until PortNumber).map { i =>
val discard = toIFU(i).bits.exception =/= ExceptionType.none || toIFU(i).bits.pmp_mmio ||
val discard = ExceptionType.hasException(toIFU(i).bits.exception) || toIFU(i).bits.pmp_mmio ||
Pbmt.isUncache(toIFU(i).bits.itlb_pbmt)
discard
}
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4 changes: 2 additions & 2 deletions src/main/scala/xiangshan/frontend/icache/IPrefetch.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -388,7 +388,7 @@ class IPrefetchPipe(implicit p: Parameters) extends IPrefetchModule {
*/
toPMP.zipWithIndex.foreach { case (p, i) =>
// if itlb has exception, paddr can be invalid, therefore pmp check can be skipped
p.valid := s1_valid // && s1_itlb_exception === ExceptionType.none
p.valid := s1_valid // !ExceptionType.hasException(s1_itlb_exception(i))
p.bits.addr := s1_req_paddr(i)
p.bits.size := 3.U // TODO
p.bits.cmd := TlbCmd.exec
Expand Down Expand Up @@ -534,7 +534,7 @@ class IPrefetchPipe(implicit p: Parameters) extends IPrefetchModule {
*/
val s2_miss = VecInit((0 until PortNumber).map { i =>
!s2_hits(i) && (if (i == 0) true.B else s2_doubleline) &&
s2_exception.take(i + 1).map(_ === ExceptionType.none).reduce(_ && _) &&
!ExceptionType.hasException(s2_exception.take(i + 1)) &&
s2_mmio.take(i + 1).map(!_).reduce(_ && _)
})

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