fix(st-ld forward): modify misaligned forward fault detection

OpenXiangShan · Dec 13, 2024 · 9d13bcf · 9d13bcf
1 parent f346d72
commit 9d13bcf
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Showing 2 changed files with 5 additions and 6 deletions.
diff --git a/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala b/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
@@ -305,8 +305,8 @@ class LoadQueueReplay(implicit p: Parameters) extends XSModule
   for (i <- 0 until LoadQueueReplaySize) {
     // dequeue
     //  FIXME: store*Ptr is not accurate
-    dataNotBlockVec(i) := isNotBefore(io.stDataReadySqPtr, blockSqIdx(i)) || stDataReadyVec(blockSqIdx(i).value) || io.sqEmpty // for better timing
-    addrNotBlockVec(i) := isNotBefore(io.stAddrReadySqPtr, blockSqIdx(i)) || !strict(i) && stAddrReadyVec(blockSqIdx(i).value) || io.sqEmpty // for better timing
+    dataNotBlockVec(i) := isAfter(io.stDataReadySqPtr, blockSqIdx(i)) || stDataReadyVec(blockSqIdx(i).value) || io.sqEmpty // for better timing
+    addrNotBlockVec(i) := isAfter(io.stAddrReadySqPtr, blockSqIdx(i)) || !strict(i) && stAddrReadyVec(blockSqIdx(i).value) || io.sqEmpty // for better timing
     // store address execute
     storeAddrInSameCycleVec(i) := VecInit((0 until StorePipelineWidth).map(w => {
       io.storeAddrIn(w).valid &&

diff --git a/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala b/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
@@ -685,14 +685,13 @@ class StoreQueue(implicit p: Parameters) extends XSModule
     //TODO But for the time being, this is the way to ensure correctness. Such a suitable opportunity to support unaligned forward.
     val unalignedMask1 = unaligned.asUInt & forwardMask1.asUInt & allocated.asUInt
     val unalignedMask2 = unaligned.asUInt & forwardMask2.asUInt & allocated.asUInt
-    val forwardPreWithUnaligned = (unalignedMask1 | unalignedMask2).asUInt.orR
 
     // make chisel happy
     val dataInvalidMask1Reg = Wire(UInt(StoreQueueSize.W))
-    dataInvalidMask1Reg := RegNext(dataInvalidMask1)
+    dataInvalidMask1Reg := RegNext(dataInvalidMask1 | unalignedMask1)
     // make chisel happy
     val dataInvalidMask2Reg = Wire(UInt(StoreQueueSize.W))
-    dataInvalidMask2Reg := RegNext(dataInvalidMask2)
+    dataInvalidMask2Reg := RegNext(dataInvalidMask2 | unalignedMask2)
     val dataInvalidMaskReg = dataInvalidMask1Reg | dataInvalidMask2Reg
 
     // If SSID match, address not ready, mark it as addrInvalid
@@ -708,7 +707,7 @@ class StoreQueue(implicit p: Parameters) extends XSModule
     val addrInvalidMaskReg = addrInvalidMask1Reg | addrInvalidMask2Reg
 
     // load_s2
-    io.forward(i).dataInvalid := RegNext(io.forward(i).dataInvalidFast) || RegNext(forwardPreWithUnaligned)
+    io.forward(i).dataInvalid := RegNext(io.forward(i).dataInvalidFast)
     // check if vaddr forward mismatched
     io.forward(i).matchInvalid := vaddrMatchFailed