hpm: fix selection logic and typo (#1618) (#2483)

Co-authored-by: Chen Xi <[email protected]>

src/main/scala/utils/PerfCounterUtils.scala

@@ -349,23 +349,20 @@ class HPerfCounter(val numPCnt: Int)(implicit p: Parameters) extends XSModule wi
   val event_op_1 = RegNext(io.hpm_event(49, 45))
   val event_op_2 = RegNext(io.hpm_event(54, 50))
 
+  def combineEvents(cnt_1: UInt, cnt_2: UInt, optype: UInt): UInt =
+    Mux(optype(0), cnt_1 & cnt_2,
+    Mux(optype(1), cnt_1 ^ cnt_2,
+    Mux(optype(2), cnt_1 + cnt_2,
+                   cnt_1 | cnt_2)))
 
-  val event_step_0 = Mux(event_op_0(0), events_incr_3.value & events_incr_2.value,
-                     Mux(event_op_0(1), events_incr_3.value ^ events_incr_2.value,
-                     Mux(event_op_0(2), events_incr_3.value + events_incr_2.value,
-                                        events_incr_3.value | events_incr_2.value)))
-  val event_step_1 = Mux(event_op_1(0), events_incr_1.value & events_incr_0.value,
-                     Mux(event_op_1(1), events_incr_1.value ^ events_incr_0.value,
-                     Mux(event_op_1(2), events_incr_1.value + events_incr_0.value,
-                                        events_incr_1.value | events_incr_0.value)))
+  val event_step_0 = combineEvents(events_incr_0.value, events_incr_1.value, event_op_0)
+  val event_step_1 = combineEvents(events_incr_2.value, events_incr_3.value, event_op_1)
 
-  val event_op_1_reg = RegNext(event_op_1)
+  // add registers to optimize the timing (like pipelines)
+  val event_op_2_reg = RegNext(event_op_2)
   val event_step_0_reg = RegNext(event_step_0)
   val event_step_1_reg = RegNext(event_step_1)
-  val selected = Mux(event_op_1_reg(0), event_step_0_reg & event_step_1_reg,
-                 Mux(event_op_1_reg(1), event_step_0_reg ^ event_step_1_reg,
-                 Mux(event_op_1_reg(2), event_step_0_reg + event_step_1_reg,
-                   event_step_0_reg | event_step_1_reg)))
+  val selected = combineEvents(event_step_0_reg, event_step_1_reg, event_op_2_reg)
 
   val perfEvents = Seq(("selected", selected))
   generatePerfEvent()

src/main/scala/xiangshan/Parameters.scala

@@ -521,4 +521,5 @@ trait HasXSParameter {
   val numCSRPCntCtrl     = 8
   val numCSRPCntLsu      = 8
   val numCSRPCntHc       = 5
+  val printEventCoding   = true
 }

src/main/scala/xiangshan/backend/CtrlBlock.scala

@@ -711,8 +711,21 @@ class CtrlBlockImp(outer: CtrlBlock)(implicit p: Parameters) extends LazyModuleI
     val perfEventsEu1     = Input(Vec(6, new PerfEvent))
   })
 
-  val allPerfEvents = Seq(decode, rename, dispatch, intDq, fpDq, lsDq, rob).flatMap(_.getPerf)
-  val hpmEvents = allPerfEvents ++ perfinfo.perfEventsEu0 ++ perfinfo.perfEventsEu1 ++ perfinfo.perfEventsRs
-  val perfEvents = HPerfMonitor(csrevents, hpmEvents).getPerfEvents
+  val perfFromUnits = Seq(decode, rename, dispatch, intDq, fpDq, lsDq, rob).flatMap(_.getPerfEvents)
+  val perfFromIO    = perfinfo.perfEventsEu0.map(x => ("perfEventsEu0", x.value)) ++
+                        perfinfo.perfEventsEu1.map(x => ("perfEventsEu1", x.value)) ++
+                        perfinfo.perfEventsRs.map(x => ("perfEventsRs", x.value))
+  val perfBlock     = Seq()
+  // let index = 0 be no event
+  val allPerfEvents = Seq(("noEvent", 0.U)) ++ perfFromUnits ++ perfFromIO ++ perfBlock
+
+  if (printEventCoding) {
+    for (((name, inc), i) <- allPerfEvents.zipWithIndex) {
+      println("CtrlBlock perfEvents Set", name, inc, i)
+    }
+  }
+
+  val allPerfInc = allPerfEvents.map(_._2.asTypeOf(new PerfEvent))
+  val perfEvents = HPerfMonitor(csrevents, allPerfInc).getPerfEvents
   generatePerfEvent()
 }

src/main/scala/xiangshan/backend/MemBlock.scala

@@ -1048,8 +1048,21 @@ class MemBlockImp(outer: MemBlock) extends LazyModuleImp(outer)
     ("ldDeqCount", ldDeqCount),
     ("stDeqCount", stDeqCount),
   )
-  val allPerfEvents = memBlockPerfEvents ++ (loadUnits ++ Seq(sbuffer, lsq, dcache)).flatMap(_.getPerfEvents)
-  val hpmEvents = allPerfEvents.map(_._2.asTypeOf(new PerfEvent)) ++ perfEventsPTW
-  val perfEvents = HPerfMonitor(csrevents, hpmEvents).getPerfEvents
+
+  val perfFromUnits = (loadUnits ++ Seq(sbuffer, lsq, dcache)).flatMap(_.getPerfEvents)
+  val perfFromPTW    = perfEventsPTW.map(x => ("perfEventsPTW", x.value))
+  val perfBlock     = Seq(("ldDeqCount", ldDeqCount),
+                          ("stDeqCount", stDeqCount))
+  // let index = 0 be no event
+  val allPerfEvents = Seq(("noEvent", 0.U)) ++ perfFromUnits ++ perfFromPTW ++ perfBlock
+
+  if (printEventCoding) {
+    for (((name, inc), i) <- allPerfEvents.zipWithIndex) {
+      println("MemBlock perfEvents Set", name, inc, i)
+    }
+  }
+
+  val allPerfInc = allPerfEvents.map(_._2.asTypeOf(new PerfEvent))
+  val perfEvents = HPerfMonitor(csrevents, allPerfInc).getPerfEvents
   generatePerfEvent()
 }

src/main/scala/xiangshan/backend/fu/CSR.scala

@@ -633,14 +633,22 @@ class CSR(implicit p: Parameters) extends FunctionUnit with HasCSRConst with PMP
                    List.fill(8)(RegInit("h8020080200".U(XLEN.W))) ++
                    List.fill(5)(RegInit("hc0300c0300".U(XLEN.W)))
   for (i <-0 until nrPerfCnts) {
-    perfEventscounten(i) := (Cat(perfEvents(i)(62),perfEvents(i)(61),(perfEvents(i)(61,60))) & priviledgeModeOH).orR
+    perfEventscounten(i) := (perfEvents(i)(63,60) & priviledgeModeOH).orR
   }
 
   val hpmEvents = Wire(Vec(numPCntHc * coreParams.L2NBanks, new PerfEvent))
   for (i <- 0 until numPCntHc * coreParams.L2NBanks) {
     hpmEvents(i) := csrio.perf.perfEventsHc(i)
   }
 
+  // print perfEvents
+  val allPerfEvents = hpmEvents.map(x => (s"Hc", x.value))
+  if (printEventCoding) {
+    for (((name, inc), i) <- allPerfEvents.zipWithIndex) {
+      println("CSR perfEvents Set", name, inc, i)
+    }
+  }
+
   val csrevents = perfEvents.slice(24, 29)
   val hpm_hc = HPerfMonitor(csrevents, hpmEvents)
   val mcountinhibit = RegInit(0.U(XLEN.W))

src/main/scala/xiangshan/frontend/Frontend.scala

@@ -342,7 +342,19 @@ class FrontendImp (outer: Frontend) extends LazyModuleImp(outer)
   pfevent.io.distribute_csr := io.csrCtrl.distribute_csr
   val csrevents = pfevent.io.hpmevent.take(8)
 
-  val allPerfEvents = Seq(ifu, ibuffer, icache, ftq, bpu).flatMap(_.getPerf)
-  override val perfEvents = HPerfMonitor(csrevents, allPerfEvents).getPerfEvents
+  val perfFromUnits = Seq(ifu, ibuffer, icache, ftq, bpu).flatMap(_.getPerfEvents)
+  val perfFromIO    = Seq()
+  val perfBlock     = Seq()
+  // let index = 0 be no event
+  val allPerfEvents = Seq(("noEvent", 0.U)) ++ perfFromUnits ++ perfFromIO ++ perfBlock
+
+  if (printEventCoding) {
+    for (((name, inc), i) <- allPerfEvents.zipWithIndex) {
+      println("Frontend perfEvents Set", name, inc, i)
+    }
+  }
+
+  val allPerfInc = allPerfEvents.map(_._2.asTypeOf(new PerfEvent))
+  override val perfEvents = HPerfMonitor(csrevents, allPerfInc).getPerfEvents
   generatePerfEvent()
 }

src/main/scala/xiangshan/frontend/icache/ICache.scala

@@ -661,7 +661,7 @@ class ICacheImp(outer: ICache) extends LazyModuleImp(outer) with HasICacheParame
 
   val perfEvents = Seq(
     ("icache_miss_cnt  ", false.B),
-    ("icache_miss_penty", BoolStopWatch(start = false.B, stop = false.B || false.B, startHighPriority = true)),
+    ("icache_miss_penalty", BoolStopWatch(start = false.B, stop = false.B || false.B, startHighPriority = true)),
   )
   generatePerfEvent()