Skip to content

Commit

Permalink
perf: add cpi and topdown rolling db (#2280)
Browse files Browse the repository at this point in the history
Add some rolling db:

* cpi rolling db
* topdown rolling db
* ipc-fuType rolling db

Others:
Add WITH_ROLLINGDB into Makefile, then: make emu WITH_ROLLINGDB=1 to enable rollingdb.
Topdown rolling db will add many table into the database. This is something a little ugly.

To sovle this:
* run emu with --dump-select-db for wanted table, not --dump-db
* TODO: enhance the RollingDB with more complicate YAXISPT that contains all the topdown signals
  • Loading branch information
Lemover authored Sep 5, 2023
1 parent d10ddd6 commit 839e551
Show file tree
Hide file tree
Showing 4 changed files with 19 additions and 0 deletions.
5 changes: 5 additions & 0 deletions Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -53,6 +53,11 @@ ifeq ($(WITH_CHISELDB),1)
override SIM_ARGS += --with-chiseldb
endif

# run emu with chisel-db
ifeq ($(WITH_ROLLINGDB),1)
override SIM_ARGS += --with-rollingdb
endif

# dynamic switch CONSTANTIN
ifeq ($(WITH_CONSTANTIN),0)
$(info disable WITH_CONSTANTIN)
Expand Down
6 changes: 6 additions & 0 deletions src/main/scala/top/ArgParser.scala
Original file line number Diff line number Diff line change
Expand Up @@ -35,6 +35,8 @@ object ArgParser {
|--fpga-platform
|--enable-difftest
|--enable-log
|--with-chiseldb
|--with-rollingdb
|--disable-perf
|--mfc
|""".stripMargin
Expand Down Expand Up @@ -76,6 +78,10 @@ object ArgParser {
nextOption(config.alter((site, here, up) => {
case DebugOptionsKey => up(DebugOptionsKey).copy(EnableChiselDB = true)
}), tail)
case "--with-rollingdb" :: tail =>
nextOption(config.alter((site, here, up) => {
case DebugOptionsKey => up(DebugOptionsKey).copy(EnableRollingDB = true)
}), tail)
case "--with-constantin" :: tail =>
nextOption(config.alter((site, here, up) => {
case DebugOptionsKey => up(DebugOptionsKey).copy(EnableConstantin = true)
Expand Down
5 changes: 5 additions & 0 deletions src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
Original file line number Diff line number Diff line change
Expand Up @@ -343,6 +343,11 @@ class Dispatch(implicit p: Parameters) extends XSModule with HasPerfEvents {

TopDownCounters.values.foreach(ctr => XSPerfAccumulate(ctr.toString(), PopCount(stallReason.map(_ === ctr.id.U))))

val robTrueCommit = WireInit(0.U(64.W))
ExcitingUtils.addSink(robTrueCommit, "ROBTrueCommit_hart" + p(XSCoreParamsKey).HartId.toString, ExcitingUtils.Perf)
TopDownCounters.values.foreach(ctr => XSPerfRolling("td_"+ctr.toString(), PopCount(stallReason.map(_ === ctr.id.U)),
robTrueCommit, 1000, clock, reset))

XSPerfHistogram("slots_fire", PopCount(thisActualOut), true.B, 0, RenameWidth+1, 1)
// Explaination: when out(0) not fire, PopCount(valid) is not meaningfull
XSPerfHistogram("slots_valid_pure", PopCount(io.enqRob.req.map(_.valid)), thisActualOut(0), 0, RenameWidth+1, 1)
Expand Down
3 changes: 3 additions & 0 deletions src/main/scala/xiangshan/backend/rob/Rob.scala
Original file line number Diff line number Diff line change
Expand Up @@ -1080,11 +1080,13 @@ class RobImp(outer: Rob)(implicit p: Parameters) extends LazyModuleImp(outer)
val commitDebugExu = deqPtrVec.map(_.value).map(debug_exuDebug(_))
val commitDebugUop = deqPtrVec.map(_.value).map(debug_microOp(_))
val commitDebugLsInfo = deqPtrVec.map(_.value).map(debug_lsInfo(_))
ExcitingUtils.addSource(ifCommitReg(trueCommitCnt), "ROBTrueCommit_hart" + p(XSCoreParamsKey).HartId.toString, ExcitingUtils.Perf)
XSPerfAccumulate("clock_cycle", 1.U)
QueuePerf(RobSize, PopCount((0 until RobSize).map(valid(_))), !allowEnqueue)
XSPerfAccumulate("commitUop", ifCommit(commitCnt))
XSPerfAccumulate("commitInstr", ifCommitReg(trueCommitCnt))
XSPerfRolling("ipc", ifCommitReg(trueCommitCnt), 1000, clock, reset)
XSPerfRolling("cpi", perfCnt = 1.U/*Cycle*/, eventTrigger = ifCommitReg(trueCommitCnt), granularity = 1000, clock, reset)
val commitIsMove = commitDebugUop.map(_.ctrl.isMove)
XSPerfAccumulate("commitInstrMove", ifCommit(PopCount(io.commits.commitValid.zip(commitIsMove).map{ case (v, m) => v && m })))
val commitMoveElim = commitDebugUop.map(_.debugInfo.eliminatedMove)
Expand Down Expand Up @@ -1127,6 +1129,7 @@ class RobImp(outer: Rob)(implicit p: Parameters) extends LazyModuleImp(outer)
for (fuType <- FuType.functionNameMap.keys) {
val fuName = FuType.functionNameMap(fuType)
val commitIsFuType = io.commits.commitValid.zip(commitDebugUop).map(x => x._1 && x._2.ctrl.fuType === fuType.U )
XSPerfRolling(s"ipc_futype_${fuName}", ifCommit(PopCount(commitIsFuType)), 1000, clock, reset)
XSPerfAccumulate(s"${fuName}_instr_cnt", ifCommit(PopCount(commitIsFuType)))
XSPerfAccumulate(s"${fuName}_latency_dispatch", ifCommit(latencySum(commitIsFuType, dispatchLatency)))
XSPerfAccumulate(s"${fuName}_latency_enq_rs", ifCommit(latencySum(commitIsFuType, enqRsLatency)))
Expand Down

0 comments on commit 839e551

Please sign in to comment.