Frontend: delete unnecessary dontTouch in frontend (#2414)

OpenXiangShan · Oct 23, 2023 · 802c33c · 802c33c
1 parent 7a8a1a5
commit 802c33c
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Showing 6 changed files with 0 additions and 33 deletions.
diff --git a/src/main/scala/xiangshan/frontend/BPU.scala b/src/main/scala/xiangshan/frontend/BPU.scala
@@ -227,7 +227,6 @@ class Predictor(implicit p: Parameters) extends XSModule with HasBPUConst with H
   def numOfStage = 3
   require(numOfStage > 1, "BPU numOfStage must be greater than 1")
   val topdown_stages = RegInit(VecInit(Seq.fill(numOfStage)(0.U.asTypeOf(new FrontendTopDownBundle))))
-  dontTouch(topdown_stages)
 
   // following can only happen on s1
   val controlRedirectBubble = Wire(Bool())
@@ -428,9 +427,6 @@ class Predictor(implicit p: Parameters) extends XSModule with HasBPUConst with H
   val full_pred_diff = WireInit(false.B)
   val full_pred_diff_stage = WireInit(0.U)
   val full_pred_diff_offset = WireInit(0.U)
-  dontTouch(full_pred_diff)
-  dontTouch(full_pred_diff_stage)
-  dontTouch(full_pred_diff_offset)
   for (i <- 0 until numDup - 1) {
     when (io.bpu_to_ftq.resp.valid &&
       ((io.bpu_to_ftq.resp.bits.s1.full_pred(i).asTypeOf(UInt()) =/= io.bpu_to_ftq.resp.bits.s1.full_pred(i+1).asTypeOf(UInt()) && io.bpu_to_ftq.resp.bits.s1.full_pred(i).hit) ||
@@ -806,12 +802,6 @@ class Predictor(implicit p: Parameters) extends XSModule with HasBPUConst with H
       branchCommittedMask.asUInt
     val updateShift    : UInt   =
       Mux(updateValid && branchValidMask.orR, PopCount(branchValidMask & shouldShiftMask), 0.U)
-    dontTouch(updateShift)
-    dontTouch(commitGHist)
-    dontTouch(commitGHistPtr)
-    dontTouch(takenMask)
-    dontTouch(branchValidMask)
-    dontTouch(branchCommittedMask)
 
     // Maintain the commitGHist
     for (i <- 0 until numBr) {

diff --git a/src/main/scala/xiangshan/frontend/Frontend.scala b/src/main/scala/xiangshan/frontend/Frontend.scala
@@ -323,7 +323,6 @@ class FrontendImp (outer: Frontend) extends LazyModuleImp(outer)
 
   io.backend.cfVec <> ibuffer.io.out
   io.backend.stallReason <> ibuffer.io.stallReason
-  dontTouch(io.backend.stallReason)
 
   instrUncache.io.req   <> ifu.io.uncacheInter.toUncache
   ifu.io.uncacheInter.fromUncache <> instrUncache.io.resp

diff --git a/src/main/scala/xiangshan/frontend/IFU.scala b/src/main/scala/xiangshan/frontend/IFU.scala
@@ -136,7 +136,6 @@ class NewIFU(implicit p: Parameters) extends XSModule
   def numOfStage = 3
   require(numOfStage > 1, "BPU numOfStage must be greater than 1")
   val topdown_stages = RegInit(VecInit(Seq.fill(numOfStage)(0.U.asTypeOf(new FrontendTopDownBundle))))
-  dontTouch(topdown_stages)
   // bubble events in IFU, only happen in stage 1
   val icacheMissBubble = Wire(Bool())
   val itlbMissBubble =Wire(Bool())

diff --git a/src/main/scala/xiangshan/frontend/Ibuffer.scala b/src/main/scala/xiangshan/frontend/Ibuffer.scala
@@ -97,10 +97,8 @@ class IBufEntry(implicit p: Parameters) extends XSBundle {
 
 class Ibuffer(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelper with HasPerfEvents {
   val io = IO(new IBufferIO)
-  dontTouch(io.stallReason)
 
   val topdown_stage = RegInit(0.U.asTypeOf(new FrontendTopDownBundle))
-  dontTouch(topdown_stage)
   topdown_stage := io.in.bits.topdown_info
   when (io.flush) {
     when (io.ControlRedirect) {
@@ -127,7 +125,6 @@ class Ibuffer(implicit p: Parameters) extends XSModule with HasCircularQueuePtrH
   val matchBubble = Wire(UInt(log2Up(TopDownCounters.NumStallReasons.id).W))
 
   matchBubble := (TopDownCounters.NumStallReasons.id - 1).U - PriorityEncoder(topdown_stage.reasons.reverse)
-  dontTouch(matchBubble)
   val matchBubbleVec = WireInit(VecInit(topdown_stage.reasons.zipWithIndex.map{case (r, i) => matchBubble === i.U}))
 
   val ibuf = Module(new SyncDataModuleTemplate(new IBufEntry, IBufSize, 2 * DecodeWidth, PredictWidth))

diff --git a/src/main/scala/xiangshan/frontend/NewFtq.scala b/src/main/scala/xiangshan/frontend/NewFtq.scala
@@ -475,7 +475,6 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
   io.bpuInfo := DontCare
 
   val topdown_stage = RegInit(0.U.asTypeOf(new FrontendTopDownBundle))
-  dontTouch(topdown_stage)
   // only driven by clock, not valid-ready
   topdown_stage := io.fromBpu.resp.bits.topdown_info
   io.toIfu.req.bits.topdown_info := topdown_stage

diff --git a/src/main/scala/xiangshan/frontend/PreDecode.scala b/src/main/scala/xiangshan/frontend/PreDecode.scala
@@ -122,23 +122,6 @@ class PreDecode(implicit p: Parameters) extends XSModule with HasPdConst{
   h_validStart_halfPlus1.map(_ := false.B)
   h_validEnd_halfPlus1.map(_ := false.B)
 
-  dontTouch(validStart_half)
-  dontTouch(validEnd_half)
-  dontTouch(h_validStart_half)
-  dontTouch(h_validEnd_half)
-  dontTouch(validStart_halfPlus1)
-  dontTouch(validEnd_halfPlus1)
-  dontTouch(h_validStart_halfPlus1)
-  dontTouch(h_validEnd_halfPlus1)
-  dontTouch(validStart_diff)
-  dontTouch(validEnd_diff)
-  dontTouch(h_validStart_diff)
-  dontTouch(h_validEnd_diff)
-  dontTouch(validStart)
-  dontTouch(validEnd)
-  dontTouch(h_validStart)
-  dontTouch(h_validEnd)
-
   val rawInsts = if (HasCExtension) VecInit((0 until PredictWidth).map(i => Cat(data(i+1), data(i))))
   else         VecInit((0 until PredictWidth).map(i => data(i)))