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fix(LoadQueueReplay): use more precise conditions for unblocking `for…
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…warding fault`

It is not necessary to check whether the storequeue entry pointed to by sqidx is complete, because this entry is the store that follows this load.
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Anzooooo committed Dec 6, 2024
1 parent da6af81 commit 80147fa
Showing 1 changed file with 2 additions and 2 deletions.
4 changes: 2 additions & 2 deletions src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
Original file line number Diff line number Diff line change
Expand Up @@ -305,8 +305,8 @@ class LoadQueueReplay(implicit p: Parameters) extends XSModule
for (i <- 0 until LoadQueueReplaySize) {
// dequeue
// FIXME: store*Ptr is not accurate
dataNotBlockVec(i) := isAfter(io.stDataReadySqPtr, blockSqIdx(i)) || stDataReadyVec(blockSqIdx(i).value) || io.sqEmpty // for better timing
addrNotBlockVec(i) := isAfter(io.stAddrReadySqPtr, blockSqIdx(i)) || !strict(i) && stAddrReadyVec(blockSqIdx(i).value) || io.sqEmpty // for better timing
dataNotBlockVec(i) := isNotBefore(io.stDataReadySqPtr, blockSqIdx(i)) || stDataReadyVec(blockSqIdx(i).value) || io.sqEmpty // for better timing
addrNotBlockVec(i) := isNotBefore(io.stAddrReadySqPtr, blockSqIdx(i)) || !strict(i) && stAddrReadyVec(blockSqIdx(i).value) || io.sqEmpty // for better timing
// store address execute
storeAddrInSameCycleVec(i) := VecInit((0 until StorePipelineWidth).map(w => {
io.storeAddrIn(w).valid &&
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