timing(StoreQueue): cmoReq.address add 1 latch (#3988)

OpenXiangShan · Dec 16, 2024 · 4fb7cc1 · 4fb7cc1
1 parent 4d53e0e
commit 4fb7cc1
Showing 1 changed file with 3 additions and 2 deletions.
diff --git a/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala b/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
@@ -797,16 +797,17 @@ class StoreQueue(implicit p: Parameters) extends XSModule
   val s_idle :: s_req :: s_resp :: s_wb :: s_wait :: Nil = Enum(5)
   val mmioState = RegInit(s_idle)
   val uncacheUop = Reg(new DynInst)
-  val uncacheVAddr = Reg(UInt(VAddrBits.W))
   val cboFlushedSb = RegInit(false.B)
   val cmoOpCode = uncacheUop.fuOpType(1, 0)
   val mmioDoReq = io.uncache.req.fire && !io.uncache.req.bits.nc
+  val cboMmioPAddr = Reg(UInt(PAddrBits.W))
   switch(mmioState) {
     is(s_idle) {
       when(RegNext(io.rob.pendingst && uop(deqPtr).robIdx === io.rob.pendingPtr && pending(deqPtr) && allocated(deqPtr) && datavalid(deqPtr) && addrvalid(deqPtr))) {
         mmioState := s_req
         uncacheUop := uop(deqPtr)
         cboFlushedSb := false.B
+        cboMmioPAddr := paddrModule.io.rdata(0)
       }
     }
     is(s_req) {
@@ -911,7 +912,7 @@ class StoreQueue(implicit p: Parameters) extends XSModule
 
   // CBO op type check can be delayed for 1 cycle,
   // as uncache op will not start in s_idle
-  val cboMmioAddr = get_block_addr(paddrModule.io.rdata(0))
+  val cboMmioAddr = get_block_addr(cboMmioPAddr)
   val deqCanDoCbo = GatedRegNext(LSUOpType.isCbo(uop(deqPtr).fuOpType) && allocated(deqPtr) && addrvalid(deqPtr))
   when (deqCanDoCbo) {
     // disable uncache channel