feat(BPU): reduce one cycle on redirect latency

OpenXiangShan · Nov 26, 2024 · 4c731f9 · 4c731f9
1 parent 3dcf15e
commit 4c731f9
Showing 1 changed file with 2 additions and 3 deletions.
diff --git a/src/main/scala/xiangshan/frontend/BPU.scala b/src/main/scala/xiangshan/frontend/BPU.scala
@@ -367,7 +367,7 @@ class Predictor(implicit p: Parameters) extends XSModule with HasBPUConst with H
   // predictors.io.out.ready := io.bpu_to_ftq.resp.ready
 
   val redirect_req    = io.ftq_to_bpu.redirect
-  val do_redirect_dup = dup_seq(RegNextWithEnable(redirect_req))
+  val do_redirect_dup = dup_seq(redirect_req)
 
   // Pipeline logic
   s2_redirect_dup.map(_ := false.B)
@@ -405,8 +405,7 @@ class Predictor(implicit p: Parameters) extends XSModule with HasBPUConst with H
     s2_fire := s2_valid && s3_components_ready && s3_ready
 
   for ((((s0_fire, s1_flush), s1_fire), s1_valid) <- s0_fire_dup zip s1_flush_dup zip s1_fire_dup zip s1_valid_dup) {
-    when(redirect_req.valid)(s1_valid := false.B)
-      .elsewhen(s0_fire)(s1_valid := true.B)
+    when(s0_fire)(s1_valid := true.B)
       .elsewhen(s1_flush)(s1_valid := false.B)
       .elsewhen(s1_fire)(s1_valid := false.B)
   }