CSR: mstatus bits 0 and 4 are read-only zeros (#2294)

src/main/scala/xiangshan/backend/fu/CSR.scala

@@ -415,16 +415,11 @@ class CSR(implicit p: Parameters) extends FunctionUnit with HasCSRConst with PMP
     GenMask(35, 32)       | // SXL and UXL cannot be changed
     GenMask(31, 23)       | // WPRI
     GenMask(16, 15)       | // XS is read-only
-    GenMask(10, 9)        | // WPRI
-    GenMask(6)            | // WPRI
-    GenMask(2)              // WPRI
-  ), 64)).asUInt
-  val mstatusMask = (~ZeroExt((
-    GenMask(XLEN - 2, 36) | // WPRI
-    GenMask(31, 23)       | // WPRI
-    GenMask(10, 9)        | // WPRI
-    GenMask(6)            | // WPRI
-    GenMask(2)              // WPRI
+    GenMask(10, 9)        | // VS, not supported yet
+    GenMask(6)            | // UBE, always little-endian (0)
+    GenMask(4)            | // WPRI
+    GenMask(2)            | // WPRI
+    GenMask(0)              // WPRI
   ), 64)).asUInt
 
   val medeleg = RegInit(UInt(XLEN.W), 0.U)
@@ -716,7 +711,7 @@ class CSR(implicit p: Parameters) extends FunctionUnit with HasCSRConst with PMP
     MaskedRegMap(Mconfigptr, mconfigptr, 0.U(XLEN.W), MaskedRegMap.Unwritable),
 
     //--- Machine Trap Setup ---
-    MaskedRegMap(Mstatus, mstatus, mstatusWMask, mstatusUpdateSideEffect, mstatusMask),
+    MaskedRegMap(Mstatus, mstatus, mstatusWMask, mstatusUpdateSideEffect),
     MaskedRegMap(Misa, misa, 0.U, MaskedRegMap.Unwritable), // now whole misa is unchangeable
     MaskedRegMap(Medeleg, medeleg, "hb3ff".U(XLEN.W)),
     MaskedRegMap(Mideleg, mideleg, "h222".U(XLEN.W)),