feat(frontend): add Pc class for frontend, in which the least signifi…

…cant bit is hardwired to zero to save area

src/main/scala/xiangshan/frontend/Pc.scala

@@ -0,0 +1,55 @@
+/***************************************************************************************
+ * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
+ * Copyright (c) 2020-2021 Peng Cheng Laboratory
+ *
+ * XiangShan is licensed under Mulan PSL v2.
+ * You can use this software according to the terms and conditions of the Mulan PSL v2.
+ * You may obtain a copy of Mulan PSL v2 at:
+ *          http://license.coscl.org.cn/MulanPSL2
+ *
+ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+ *
+ * See the Mulan PSL v2 for more details.
+ ***************************************************************************************/
+
+package xiangshan.frontend
+
+import chisel3._
+import chisel3.util._
+import org.chipsalliance.cde.config.Parameters
+import xiangshan.XSBundle
+
+class Pc(implicit p: Parameters) extends XSBundle {
+  val pc: UInt = UInt((VAddrBits - 1).W)
+
+  def len: Int = VAddrBits
+
+  def apply(): UInt = Cat(pc, 0.U(1.W))
+
+  def apply(x: Int): Bool = apply()(x)
+
+  def apply(x: Int, y: Int): UInt = apply()(x, y)
+
+  def :=(x: UInt): Unit = pc := x(VAddrBits - 1, 1)
+
+  def +(offset: UInt): UInt = apply() + offset
+
+  def ===(that: Pc): Bool = pc === that.pc
+
+  def =/=(that: Pc): Bool = pc =/= that.pc
+}
+
+object Pc {
+  def apply()(implicit p: Parameters): Pc = new Pc
+}
+
+object PcInit {
+  def apply(fullPc: UInt)(implicit p: Parameters): Pc = {
+    val pc = Wire(new Pc)
+    assert(fullPc.getWidth == pc.len)
+    pc := fullPc
+    pc
+  }
+}