fix(IFU): mark mmio mismatch exception only on the second line (#3963)

When mmio mismatch happens, we can still fetch inst from the first page.
So we can just mark the exception on the second cacheline.

Also fixes a bug: when itlb page fault occurs only on the second page,
PMP check may return incorrect results (as the input paddr may be
incorrect), on which request the mmio mismatch check should not be
performed. (Here we still perform the check, but the result will be
ignored, since itlb exception has higher priority in
`ExceptionType.merge`)

src/main/scala/xiangshan/frontend/IFU.scala

@@ -394,16 +394,19 @@ class NewIFU(implicit p: Parameters) extends XSModule
   val f2_isForVSnonLeafPTE = fromICache.bits.isForVSnonLeafPTE
 
   // FIXME: raise af if one fetch block crosses the cacheable-noncacheable boundary, might not correct
-  val f2_mmio_mismatch_exception = VecInit(Seq.fill(2)(Mux(
-    // not double-line, skip check
-    !fromICache.bits.doubleline || (
-      // is double-line, ask for consistent pmp_mmio and itlb_pbmt value
-      fromICache.bits.pmp_mmio(0) === fromICache.bits.pmp_mmio(1) &&
-        fromICache.bits.itlb_pbmt(0) === fromICache.bits.itlb_pbmt(1)
-    ),
-    ExceptionType.none,
-    ExceptionType.af
-  )))
+  val f2_mmio_mismatch_exception = VecInit(Seq(
+    ExceptionType.none, // mark the exception only on the second line
+    Mux(
+      // not double-line, skip check
+      !fromICache.bits.doubleline || (
+        // is double-line, ask for consistent pmp_mmio and itlb_pbmt value
+        fromICache.bits.pmp_mmio(0) === fromICache.bits.pmp_mmio(1) &&
+          fromICache.bits.itlb_pbmt(0) === fromICache.bits.itlb_pbmt(1)
+      ),
+      ExceptionType.none,
+      ExceptionType.af
+    )
+  ))
 
   // merge exceptions
   val f2_exception = ExceptionType.merge(f2_exception_in, f2_mmio_mismatch_exception)