chore: add licenses to files of memory encryption modules

OpenXiangShan · Dec 4, 2024 · 2e62b98 · 2e62b98
1 parent c13d9d6
commit 2e62b98
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Showing 3 changed files with 31 additions and 1 deletion.
diff --git a/src/main/scala/device/MemEncrypt.scala b/src/main/scala/device/MemEncrypt.scala
@@ -1,3 +1,18 @@
+/***************************************************************************************
+* Copyright (c) 2024 Institute of Information Engineering, Chinese Academy of Sciences
+*
+* XiangShan is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*          http://license.coscl.org.cn/MulanPSL2
+*
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+*
+* See the Mulan PSL v2 for more details.
+***************************************************************************************/
+
 // See LICENSE.SiFive for license details.
 
 package device

diff --git a/src/main/scala/device/MemEncryptUtil.scala b/src/main/scala/device/MemEncryptUtil.scala
@@ -1,3 +1,18 @@
+/***************************************************************************************
+* Copyright (c) 2024 Institute of Information Engineering, Chinese Academy of Sciences
+*
+* XiangShan is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*          http://license.coscl.org.cn/MulanPSL2
+*
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+*
+* See the Mulan PSL v2 for more details.
+***************************************************************************************/
+
 // See LICENSE.SiFive for license details.
 
 package device

diff --git a/src/main/scala/system/SoC.scala b/src/main/scala/system/SoC.scala
@@ -210,7 +210,7 @@ trait HaveAXI4MemPort {
   this: BaseSoC =>
   val device = new MemoryDevice
   // 48-bit physical address
-  val memRange = AddressSet(0x00000000L, 0x1fffffffffffffL).subtract(AddressSet(0x0L, 0x7fffffffL))
+  val memRange = AddressSet(0x00000000L, 0xffffffffffffL).subtract(AddressSet(0x0L, 0x7fffffffL))
   val memAXI4SlaveNode = AXI4SlaveNode(Seq(
     AXI4SlavePortParameters(
       slaves = Seq(