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OpenXiangShan / XiangShan Public

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EMU Test

area(Lsq): compress rar/raw paddr and remove sq useless regs (#3976) #9537

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area(Lsq): compress rar/raw paddr and remove sq useless regs (#3976)

area(Lsq): compress rar/raw paddr and remove sq useless regs (#3976) #9537

Summary
Jobs
Run details
- Usage
- Workflow file

Usage Workflow file

Generate Verilog

Generate Verilog

succeeded Dec 10, 2024 in 1h 53m 58s

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