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OpenXiangShan / XiangShan Public

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EMU Test

area(Lsq): compress rar/raw paddr and remove sq useless regs #9436

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area(Lsq): compress rar/raw paddr and remove sq useless regs

area(Lsq): compress rar/raw paddr and remove sq useless regs #9436

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- Usage
- Workflow file

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Generate Verilog

succeeded Dec 4, 2024 in 1h 45m 10s

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