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timing(csr): add 1 cycle to csr read/write and select highest interrupt priority #9369

timing(csr): add 1 cycle to csr read/write and select highest interrupt priority

timing(csr): add 1 cycle to csr read/write and select highest interrupt priority #9369

Triggered via pull request November 28, 2024 15:11
Status Success
Total duration 5h 14m 30s
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emu.yml

on: pull_request
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1 warning
Changes Detection
Unexpected input(s) 'predicate-quantifier', valid inputs are ['token', 'working-directory', 'ref', 'base', 'filters', 'list-files', 'initial-fetch-depth']