timing(csr): add 1 cycle to csr read/write and select highest interrupt priority #9367
Triggered via pull request
November 28, 2024 10:17
Status
Success
Total duration
5h 22m 52s
Artifacts
–
emu.yml
on: pull_request
Changes Detection
4s
Generate Verilog
3h 31m
EMU - Basics
5h 22m
EMU - CHI
1h 14m
EMU - Performance
3h 46m
EMU - MC
4h 56m
SIMV - Basics
5h 16m
Check Submodules
29s
Annotations
1 warning
Changes Detection
Unexpected input(s) 'predicate-quantifier', valid inputs are ['token', 'working-directory', 'ref', 'base', 'filters', 'list-files', 'initial-fetch-depth']
|