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timing(csr): add 1 cycle to csr read/write and select highest interrupt priority #9345

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timing(csr): add 1 cycle to csr read/write and select highest interrupt priority

timing(csr): add 1 cycle to csr read/write and select highest interrupt priority #9345

Triggered via pull request November 27, 2024 10:36
@sinceforYysinceforYy
synchronize #3946
sinceforYy:fix-csr-reg
Status Failure
Total duration 5h 13m 37s
Artifacts –

emu.yml

on: pull_request
Changes Detection
4s
Changes Detection
Generate Verilog
1h 2m
Generate Verilog
EMU - Basics
1h 23m
EMU - Basics
EMU - CHI
39m 28s
EMU - CHI
EMU - Performance
4h 3m
EMU - Performance
EMU - MC
2h 13m
EMU - MC
SIMV - Basics
5h 13m
SIMV - Basics
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4 errors and 1 warning
EMU - CHI
Process completed with exit code 1.
Generate Verilog
Process completed with exit code 1.
EMU - Basics
Process completed with exit code 1.
EMU - MC
Process completed with exit code 1.
Changes Detection
Unexpected input(s) 'predicate-quantifier', valid inputs are ['token', 'working-directory', 'ref', 'base', 'filters', 'list-files', 'initial-fetch-depth']