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timing(csr): add 1 cycle to csr read/write and select highest interrupt priority #9344

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timing(csr): add 1 cycle to csr read/write and select highest interrupt priority

timing(csr): add 1 cycle to csr read/write and select highest interrupt priority #9344

Triggered via pull request November 27, 2024 09:38
@sinceforYysinceforYy
synchronize #3946
sinceforYy:fix-csr-reg
Status Failure
Total duration 1h 2m 25s
Artifacts –

emu.yml

on: pull_request
Changes Detection
4s
Changes Detection
Generate Verilog
33m 14s
Generate Verilog
EMU - Basics
1h 1m
EMU - Basics
EMU - CHI
30m 43s
EMU - CHI
EMU - Performance
1h 2m
EMU - Performance
EMU - MC
53m 51s
EMU - MC
SIMV - Basics
20m 13s
SIMV - Basics
Check Submodules
21s
Check Submodules
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6 errors and 1 warning
SIMV - Basics
Process completed with exit code 1.
EMU - CHI
Process completed with exit code 1.
Generate Verilog
Process completed with exit code 1.
EMU - MC
Process completed with exit code 2.
EMU - Basics
Process completed with exit code 2.
EMU - Performance
Process completed with exit code 2.
Changes Detection
Unexpected input(s) 'predicate-quantifier', valid inputs are ['token', 'working-directory', 'ref', 'base', 'filters', 'list-files', 'initial-fetch-depth']