timing(csr): add 1 cycle to csr read/write and select highest interrupt priority #9339
Triggered via pull request
November 27, 2024 07:38
sinceforYy
Status
Cancelled
Total duration
1h 46m 53s
Artifacts
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emu.yml
on: pull_request
Changes Detection
3s
Generate Verilog
55m 52s
EMU - Basics
1h 46m
EMU - CHI
29m 38s
EMU - Performance
1h 46m
EMU - MC
1h 46m
SIMV - Basics
1h 46m
Check Submodules
19s
Annotations
10 errors and 1 warning
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EMU - CHI
Process completed with exit code 1.
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Generate Verilog
Process completed with exit code 1.
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SIMV - Basics
The run was canceled by @sinceforYy.
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SIMV - Basics
The operation was canceled.
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EMU - Performance
The run was canceled by @sinceforYy.
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EMU - Performance
The operation was canceled.
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EMU - Basics
The run was canceled by @sinceforYy.
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EMU - Basics
The operation was canceled.
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EMU - MC
The run was canceled by @sinceforYy.
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EMU - MC
The operation was canceled.
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Changes Detection
Unexpected input(s) 'predicate-quantifier', valid inputs are ['token', 'working-directory', 'ref', 'base', 'filters', 'list-files', 'initial-fetch-depth']
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