#9 phase currents

CM4/Core/Src/main.c

@@ -69,6 +69,7 @@ const osThreadAttr_t defaultTask_attributes = {
 
 /* Private function prototypes -----------------------------------------------*/
 static void MX_GPIO_Init(void);
+static void MX_DMA_Init(void);
 static void MX_FDCAN1_Init(void);
 static void MX_QUADSPI_Init(void);
 static void MX_USB_OTG_FS_PCD_Init(void);
@@ -124,6 +125,7 @@ int main(void)
 
   /* Initialize all configured peripherals */
   MX_GPIO_Init();
+  MX_DMA_Init();
   MX_FDCAN1_Init();
   MX_QUADSPI_Init();
   MX_USB_OTG_FS_PCD_Init();
@@ -381,6 +383,17 @@ static void MX_USB_OTG_FS_PCD_Init(void)
 
 }
 
+/**
+  * Enable DMA controller clock
+  */
+static void MX_DMA_Init(void)
+{
+
+  /* DMA controller clock enable */
+  __HAL_RCC_DMA1_CLK_ENABLE();
+
+}
+
 /**
   * @brief GPIO Initialization Function
   * @param None

CM7/Core/Inc/gatedriver.h

@@ -3,32 +3,60 @@
 
 #include "cmsis_os.h"
 #include "stm32h7xx.h"
+#include "stm32h7xx_hal.h"
 #include <stdbool.h>
 #include <stdint.h>
 
-enum phase{
-    U,
-    V,
-    W
+/*
+ * Note that these phases readings should ALWAYS be mapped to the corresponding indices
+ * Ensure the ADC DMA is mapped the same across boards
+ */
+enum {
+    GATEDRV_PHASE_U,
+    GATEDRV_PHASE_V,
+    GATEDRV_PHASE_W,
+    GATEDRV_NUM_PHASES
 };
 
+enum {
+    GATEDRV_DC_CURRENT = GATEDRV_NUM_PHASES, /* Keep index rolling from phase enum */
+    GATEDRV_IGBT_TEMP,
+    GATEDRV_SIZE_OF_ADC_DMA
+};
+
+/* Definition of gatedriver struct */
 typedef struct {
 	TIM_HandleTypeDef* tim;
     osMutexId_t* tim_mutex;
-    TIM_OC_InitTypeDef* pPWMConfig;
-	uint32_t pulses[];
+    TIM_OC_InitTypeDef* pwm_cfg;
+	uint32_t pulses[GATEDRV_NUM_PHASES];
+
+    ADC_HandleTypeDef *hdma_adc;
+	SPI_HandleTypeDef *adc_spi;
+    uint32_t intern_adc_buffer[GATEDRV_SIZE_OF_ADC_DMA];
+
+    osMutexId_t* tim_mutex_mutex;
+    osMutexAttr_t tim_mutex_attr;
+    osMutexId_t* ext_adc_mutex;
+    osMutexAttr_t ext_adc_mutex_attr;
 } gatedriver_t;
 
-gatedriver_t* gatedrv_init(TIM_HandleTypeDef* tim);
+/* initialize a new gatedriver */
+gatedriver_t* gatedrv_init(TIM_HandleTypeDef* tim, ADC_HandleTypeDef *hdma_adc, SPI_HandleTypeDef *adc_spi);
 
+/* read the dc voltage (V) */
 int16_t gatedrv_read_dc_voltage(gatedriver_t* drv);
 
+/* read the dc current (A) */
 int16_t gatedrv_read_dc_current(gatedriver_t* drv);
 
 /* Note: This has to atomically write to ALL PWM registers */
-//TODO: mechanism for PWM synchronization
 int16_t gatedrv_write_pwm(gatedriver_t* drv, float duty_cycles[]);
 
+/* read the internal IGBT temp */
 int16_t gatedrv_read_igbt_temp(gatedriver_t* drv);
 
+/* read the currents of each phase */
+void gatedrv_get_phase_currents(gatedriver_t* drv, int16_t current_buf[GATEDRV_NUM_PHASES]);
+
 #endif /* GATEDRIVER_H */

CM7/Core/Inc/stm32h7xx_it.h

@@ -53,6 +53,8 @@ void BusFault_Handler(void);
 void UsageFault_Handler(void);
 void DebugMon_Handler(void);
 void SysTick_Handler(void);
+void DMA1_Stream0_IRQHandler(void);
+void DMA1_Stream2_IRQHandler(void);
 /* USER CODE BEGIN EFP */
 
 /* USER CODE END EFP */

CM7/Core/Src/gatedriver.c

@@ -1,4 +1,3 @@
-
 #include "gatedriver.h"
 #include "stm32h7xx.h"
 #include <assert.h>
@@ -7,19 +6,6 @@
 
 #define  PERIOD_VALUE		(uint32_t)(2000 - 1)
 
-const static osMutexAttr_t gatedrv_tim_mutex_attr;
-
-//TODO: Look up STM callback func pointer for ADCs
-static void gatedrv_current_adc_cb(gatedriver_t* drv)
-{
-
-}
-
-static void gatedrv_voltage_adc_cb(gatedriver_t* drv)
-{
-
-}
-
 static void gatedrv_ready_cb(gatedriver_t* drv)
 {
 
@@ -35,47 +21,60 @@ static void gatedrv_fault_cb(gatedriver_t* drv)
 
 }
 
-gatedriver_t* gatedrv_init(TIM_HandleTypeDef* tim)
+gatedriver_t* gatedrv_init(TIM_HandleTypeDef* tim, ADC_HandleTypeDef *hdma_adc, SPI_HandleTypeDef *adc_spi)
 {
 	/* Assert hardware params */
 	assert(tim);
+	assert(hdma_adc);
+	assert(adc_spi);
 
 	/* Create MPU struct */
 	gatedriver_t* gatedriver = malloc(sizeof(gatedriver_t));
 	assert(gatedriver);
 
 	/* Set interfaces */
 	gatedriver->tim			= tim;
-
+	gatedriver->hdma_adc	= hdma_adc;
+	gatedriver->adc_spi		= adc_spi;
+
 	/* Init hardware */
 	tim->Init.Prescaler			= 0;
 	tim->Init.Period			= PERIOD_VALUE;
 	tim->Init.ClockDivision		= 0;
 	tim->Init.CounterMode		= TIM_COUNTERMODE_UP;
 	tim->Init.RepetitionCounter	= 0;
-	if(HAL_TIM_PWM_Init(tim) != HAL_OK) {
-		// TODO: how to handle this error?
-	}
+	assert(HAL_TIM_PWM_Init(tim) != HAL_OK);
 
 	/* Common configuration for all PWM channels */
-	TIM_OC_InitTypeDef PWMConfig;
-	PWMConfig.OCMode       = TIM_OCMODE_PWM1;
-	PWMConfig.OCPolarity   = TIM_OCPOLARITY_HIGH;
-	PWMConfig.OCNPolarity  = TIM_OCNPOLARITY_HIGH;
-	PWMConfig.OCIdleState  = TIM_OCIDLESTATE_SET;
-	PWMConfig.OCNIdleState = TIM_OCNIDLESTATE_RESET;
-	PWMConfig.OCFastMode   = TIM_OCFAST_DISABLE;
-	gatedriver->pPWMConfig = &PWMConfig;
+	TIM_OC_InitTypeDef pwm_cfg;
+	pwm_cfg.OCMode       = TIM_OCMODE_PWM1;
+	pwm_cfg.OCPolarity   = TIM_OCPOLARITY_HIGH;
+	pwm_cfg.OCNPolarity  = TIM_OCNPOLARITY_HIGH;
+	pwm_cfg.OCIdleState  = TIM_OCIDLESTATE_SET;
+	pwm_cfg.OCNIdleState = TIM_OCNIDLESTATE_RESET;
+	pwm_cfg.OCFastMode   = TIM_OCFAST_DISABLE;
+	gatedriver->pwm_cfg = &pwm_cfg;
+
+	/* Configure DMA */
+	assert(HAL_ADC_Start_DMA(gatedriver->hdma_adc, gatedriver->intern_adc_buffer, GATEDRV_SIZE_OF_ADC_DMA));
 
 	/* Create Mutexes */
-	gatedriver->tim_mutex = osMutexNew(&gatedrv_tim_mutex_attr);
+	gatedriver->tim_mutex = osMutexNew(&gatedriver->tim_mutex_attr);
 	assert(gatedriver->tim_mutex);
 
-	//TODO: Link interrupts to callbacks
+	gatedriver->ext_adc_mutex = osMutexNew(&gatedriver->ext_adc_mutex_attr);
+	assert(gatedriver->ext_adc_mutex);
 
 	return gatedriver;
 }
 
+void gatedrv_get_phase_currents(gatedriver_t* drv, int16_t current_buf[GATEDRV_NUM_PHASES])
+{
+	current_buf[GATEDRV_PHASE_U] = drv->intern_adc_buffer[GATEDRV_PHASE_U];
+	current_buf[GATEDRV_PHASE_V] = drv->intern_adc_buffer[GATEDRV_PHASE_V];
+	current_buf[GATEDRV_PHASE_W] = drv->intern_adc_buffer[GATEDRV_PHASE_W];
+}
+
 int16_t gatedrv_read_dc_voltage(gatedriver_t* drv)
 {
 
@@ -87,7 +86,7 @@ int16_t gatedrv_read_dc_current(gatedriver_t* drv)
 }
 
 /* Note: This has to atomically write to ALL PWM registers */
-int16_t gatedrv_write_pwm(gatedriver_t* drv, float duty_cycles[])
+int16_t gatedrv_write_pwm(gatedriver_t* drv, float duty_cycles[GATEDRV_NUM_PHASES])
 {
 	/* Acquiring mutex lock */
 	osStatus_t mut_stat = osMutexAcquire(drv->tim_mutex, osWaitForever);
@@ -102,8 +101,8 @@ int16_t gatedrv_write_pwm(gatedriver_t* drv, float duty_cycles[])
 	pulses[2] = (uint32_t) (duty_cycles[2] * PERIOD_VALUE / 100);
 
 	/* Getting PWM channel config */
-	TIM_OC_InitTypeDef* config = drv->pPWMConfig;
-	
+	TIM_OC_InitTypeDef* config = drv->pwm_cfg;
+
 	/* Attempting to set channel 1 */
 	config->Pulse = pulses[0];
 	if(HAL_TIM_PWM_ConfigChannel(drv->tim, config, TIM_CHANNEL_1) != HAL_OK)