Skip to content

Commit

Permalink
Merge pull request aws#341 from sbarillet/master
Browse files Browse the repository at this point in the history
fixed encryption issue with verilog file extension (.v)
  • Loading branch information
kristopk authored May 30, 2017
2 parents 2d0c60e + 4bfd3a2 commit 10222be
Show file tree
Hide file tree
Showing 6 changed files with 6 additions and 6 deletions.
Original file line number Diff line number Diff line change
Expand Up @@ -238,7 +238,7 @@ puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Reading developer's
# Reading the .sv and .v files, as proper designs would not require
# reading .v, .vh, nor .inc files

read_verilog -sv [ glob $ENC_SRC_DIR/*.?v ]
read_verilog -sv [ glob $ENC_SRC_DIR/*.{v,sv} ]

#---- End of section replaced by User ----

Expand Down
2 changes: 1 addition & 1 deletion hdk/cl/examples/cl_dram_dma/build/scripts/encrypt.tcl
Original file line number Diff line number Diff line change
Expand Up @@ -63,7 +63,7 @@ file copy -force $UNUSED_TEMPLATES_DIR/unused_sh_bar1_template.inc $TARGET_DIR
exec chmod +w {*}[glob $TARGET_DIR/*]

# encrypt .v/.sv/.vh/inc as verilog files
encrypt -k $HDK_SHELL_DIR/build/scripts/vivado_keyfile.txt -lang verilog [glob -nocomplain -- $TARGET_DIR/*.?v] [glob -nocomplain -- $TARGET_DIR/*.vh] [glob -nocomplain -- $TARGET_DIR/*.inc]
encrypt -k $HDK_SHELL_DIR/build/scripts/vivado_keyfile.txt -lang verilog [glob -nocomplain -- $TARGET_DIR/*.{v,sv}] [glob -nocomplain -- $TARGET_DIR/*.vh] [glob -nocomplain -- $TARGET_DIR/*.inc]

# encrypt *vhdl files
encrypt -k $HDK_SHELL_DIR/build/scripts/vivado_vhdl_keyfile.txt -lang vhdl -quiet [ glob -nocomplain -- $TARGET_DIR/*.vhd? ]
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -180,7 +180,7 @@ puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Reading developer's
# Reading the .sv and .v files, as proper designs would not require
# reading .v, .vh, nor .inc files

read_verilog -sv [glob $ENC_SRC_DIR/*.?v]
read_verilog -sv [glob $ENC_SRC_DIR/*.{v,sv}]

#---- End of section replaced by User ----

Expand Down
2 changes: 1 addition & 1 deletion hdk/cl/examples/cl_hello_world/build/scripts/encrypt.tcl
Original file line number Diff line number Diff line change
Expand Up @@ -51,7 +51,7 @@ file copy -force $UNUSED_TEMPLATES_DIR/unused_flr_template.inc $TARGET_DI
exec chmod +w {*}[glob $TARGET_DIR/*]

# encrypt .v/.sv/.vh/inc as verilog files
encrypt -k $HDK_SHELL_DIR/build/scripts/vivado_keyfile.txt -lang verilog [glob -nocomplain -- $TARGET_DIR/*.?v] [glob -nocomplain -- $TARGET_DIR/*.vh] [glob -nocomplain -- $TARGET_DIR/*.inc]
encrypt -k $HDK_SHELL_DIR/build/scripts/vivado_keyfile.txt -lang verilog [glob -nocomplain -- $TARGET_DIR/*.{v,sv}] [glob -nocomplain -- $TARGET_DIR/*.vh] [glob -nocomplain -- $TARGET_DIR/*.inc]

# encrypt *vhdl files
encrypt -k $HDK_SHELL_DIR/build/scripts/vivado_vhdl_keyfile.txt -lang vhdl -quiet [ glob -nocomplain -- $TARGET_DIR/*.vhd? ]
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -112,7 +112,7 @@ puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Reading developer's
# Reading the .sv and .v files, as proper designs would not require
# reading .v, .vh, nor .inc files

read_verilog -sv [glob $ENC_SRC_DIR/*.?v]
read_verilog -sv [glob $ENC_SRC_DIR/*.{v,sv}]

#---- End of section replaced by User ----

Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -173,7 +173,7 @@ puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Reading developer's
# Reading the .sv and .v files, as proper designs would not require
# reading .v, .vh, nor .inc files

read_verilog -sv [glob $ENC_SRC_DIR/*.?v]
read_verilog -sv [glob $ENC_SRC_DIR/*.{v,sv}]

#---- End of section replaced by User ----

Expand Down

0 comments on commit 10222be

Please sign in to comment.