fixed verilog file source parsing issue

hdk/cl/examples/cl_dram_dma/build/scripts/create_dcp_from_cl.tcl

@@ -238,7 +238,7 @@ puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Reading developer's
 # Reading the .sv and .v files, as proper designs would not require
 # reading .v, .vh, nor .inc files
 
-read_verilog -sv [ glob $ENC_SRC_DIR/*.?v ]
+read_verilog -sv [ glob $ENC_SRC_DIR/*.{v,sv} ]
 
 #---- End of section replaced by User ----
 

hdk/cl/examples/cl_hello_world/build/scripts/create_dcp_from_cl.tcl

@@ -180,7 +180,7 @@ puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Reading developer's
 # Reading the .sv and .v files, as proper designs would not require
 # reading .v, .vh, nor .inc files
 
-read_verilog -sv  [glob $ENC_SRC_DIR/*.?v] 
+read_verilog -sv  [glob $ENC_SRC_DIR/*.{v,sv}] 
 
 #---- End of section replaced by User ----
 

hdk/common/shell_v032117d7/new_cl_template/build/scripts/create_dcp_from_cl.tcl

@@ -112,7 +112,7 @@ puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Reading developer's
 # Reading the .sv and .v files, as proper designs would not require
 # reading .v, .vh, nor .inc files
 
-read_verilog -sv  [glob $ENC_SRC_DIR/*.?v] 
+read_verilog -sv  [glob $ENC_SRC_DIR/*.{v,sv}] 
 
 #---- End of section replaced by User ----
 

hdk/common/shell_v04151701/new_cl_template/build/scripts/create_dcp_from_cl.tcl

@@ -173,7 +173,7 @@ puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Reading developer's
 # Reading the .sv and .v files, as proper designs would not require
 # reading .v, .vh, nor .inc files
 
-read_verilog -sv  [glob $ENC_SRC_DIR/*.?v] 
+read_verilog -sv  [glob $ENC_SRC_DIR/*.{v,sv}] 
 
 #---- End of section replaced by User ----