init RAM from file

clkr/Top.vhd

@@ -13,6 +13,10 @@ ARCHITECTURE Behavioral OF TOP IS
 	SIGNAL RAM_WR : STD_LOGIC;
 	SIGNAL RAM_CLOCK : STD_LOGIC; 
 	SIGNAL RAM_DATA_OUT : STD_LOGIC_VECTOR(7 DOWNTO 0);
+
+	-- RAM initialization signal
+	SIGNAL IS_RAM_INITALIZED : STD_LOGIC := '0';
+	SIGNAL PERFORM_RAM_INIT : STD_LOGIC := '0';
 
 	-- Clock signal for testing purposes
 	SIGNAL CLK : STD_LOGIC := '0';
@@ -27,6 +31,13 @@ ARCHITECTURE Behavioral OF TOP IS
 		RAM_DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) -- Data output of RAM
 	);
 	END COMPONENT;
+
+	COMPONENT RAM_INIT 
+	PORT (
+		CLK : IN STD_LOGIC;
+		PERFORM_INIT : IN STD_LOGIC
+	);
+	END COMPONENT;
 
 BEGIN
 
@@ -37,7 +48,19 @@ BEGIN
 								  RAM_CLOCK => CLK,
 								  RAM_DATA_OUT => RAM_DATA_OUT
 								  );
-
+
+	-- Initialize RAM
+	RAM_INITIALIZE: RAM_INIT PORT MAP (CLK => CLK,
+								  PERFORM_INIT => PERFORM_RAM_INIT
+								  );
+
+	PROCESS 
+	BEGIN
+		IF IS_RAM_INITALIZED = '0'
+		THEN
+			PERFORM_RAM_INIT <= '1';
+		END IF;
+	END PROCESS;
 
 	-- Create testing signal
 	PROCESS

clkr/clkr.xise

@@ -16,19 +16,19 @@
 
   <files>
     <file xil_pn:name="Top.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
     </file>
     <file xil_pn:name="RAM.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
     </file>
     <file xil_pn:name="RegFile.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
     </file>
     <file xil_pn:name="RamInit.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
     </file>
   </files>
@@ -310,7 +310,7 @@
     <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
-    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
+    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-200X" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>

clkr/fuse.log

@@ -3,18 +3,23 @@ ISim P.20131013 (signature 0x7708f090)
 Number of CPUs detected in this system: 8
 Turning on mult-threading, number of parallel sub-compilation jobs: 16 
 Determining compilation order of HDL files
+Parsing VHDL file "C:/Users/sina/Desktop/HyperDbg/clkr/clkr/RamInit.vhd" into library work
 Parsing VHDL file "C:/Users/sina/Desktop/HyperDbg/clkr/clkr/RAM.vhd" into library work
 Parsing VHDL file "C:/Users/sina/Desktop/HyperDbg/clkr/clkr/Top.vhd" into library work
+WARNING:HDLCompiler:1369 - "C:/Users/sina/Desktop/HyperDbg/clkr/clkr/Top.vhd" Line 57: Possible infinite loop; process does not have a wait statement
 Starting static elaboration
 Completed static elaboration
 Compiling package standard
 Compiling package std_logic_1164
 Compiling package numeric_std
+Compiling package textio
+Compiling package std_logic_textio
 Compiling architecture behavioral of entity RAM [ram_default]
+Compiling architecture behavioral of entity RAM_INIT [ram_init_default]
 Compiling architecture behavioral of entity top
 Time Resolution for simulation is 1ps.
 Waiting for 1 sub-compilation(s) to finish...
-Compiled 6 VHDL Units
+Compiled 10 VHDL Units
 Built simulation executable C:/Users/sina/Desktop/HyperDbg/clkr/clkr/TOP_isim_beh.exe
-Fuse Memory Usage: 36584 KB
-Fuse CPU Usage: 546 ms
+Fuse Memory Usage: 36456 KB
+Fuse CPU Usage: 640 ms

clkr/fuse.xmsgs

@@ -5,5 +5,8 @@
      behavior or data corruption.  It is strongly advised that
      users do not edit the contents of this file. -->
 <messages>
+<msg type="warning" file="HDLCompiler" num="1369" delta="unknown" >"C:/Users/sina/Desktop/HyperDbg/clkr/clkr/Top.vhd" Line 57: Possible infinite loop; process does not have a wait statement
+</msg>
+
 </messages>
 

clkr/input.dat

@@ -0,0 +1,5 @@
+55
+85
+69
+55
+55

clkr/isim.log

@@ -27,4 +27,4 @@ Time resolution is 1 ps
 # wave add /
 # run 1000 ns
 Simulator is doing circuit initialization process.
-Finished circuit initialization process.
+Stopped at time : 0 fs : File "C:/Users/sina/Desktop/HyperDbg/clkr/clkr/Top.vhd" Line 59