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read RAM from file (testbench)
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@SinaKarvandi
SinaKarvandi committed Jul 13, 2022
1 parent 4f97732 commit 1d328a9
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Binary file added clkr/RAM_INIT_isim_beh.exe
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34 changes: 34 additions & 0 deletions clkr/RamInit.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;

LIBRARY STD;

USE STD.TEXTIO.ALL;

ENTITY RAM_INIT IS
PORT (
CLK : IN STD_LOGIC;
PERFORM_INIT : IN STD_LOGIC
);
END RAM_INIT;

ARCHITECTURE Behavioral OF RAM_INIT IS

FILE FIN : TEXT OPEN READ_MODE IS "input.dat";

BEGIN

PROCESS (CLK)
VARIABLE RD_LINE : LINE;
VARIABLE HEX : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
IF PERFORM_INIT = '1' THEN
WHILE NOT ENDFILE(FIN) LOOP
readline(FIN, RD_LINE);
hread(RD_LINE, HEX);
END LOOP;
END IF;
END PROCESS;

END Behavioral;
56 changes: 29 additions & 27 deletions clkr/RegFile.vhd
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;

ENTITY register_file IS
ENTITY REGISTER_FILE IS
PORT (
outA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
outB : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
input : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
writeEnable : IN STD_LOGIC;
regASel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
regBSel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
writeRegSel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
clk : IN STD_LOGIC
OUT_REG_A : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
OUT_REG_B : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
INPUT_VAL : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
WRITE_ENABLE : IN STD_LOGIC;
SEL_REG_A : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
SEL_REG_B : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
WRITE_REG_SEL : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
CLK : IN STD_LOGIC
);
END register_file;
END REGISTER_FILE;

ARCHITECTURE behavioral OF register_file IS
TYPE registerFile IS ARRAY(0 TO 15) OF STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL registers : registerFile;
ARCHITECTURE Behavioral OF REGISTER_FILE IS
TYPE REGISTER_FILE_TYPE IS ARRAY(0 TO 15) OF STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL REGISTERS : REGISTER_FILE_TYPE;
BEGIN

regFile : PROCESS (clk) IS
RegFile : PROCESS (CLK) IS
BEGIN
IF rising_edge(clk) THEN
IF rising_edge(CLK) THEN

-- Read A and B before bypass
outA <= registers(to_integer(unsigned(regASel)));
outB <= registers(to_integer(unsigned(regBSel)));
OUT_REG_A <= registers(to_integer(unsigned(SEL_REG_A)));
OUT_REG_B <= registers(to_integer(unsigned(SEL_REG_B)));

-- Write and bypass
IF writeEnable = '1' THEN
registers(to_integer(unsigned(writeRegSel))) <= input; -- Write
IF regASel = writeRegSel THEN -- Bypass for read A
outA <= input;
IF WRITE_ENABLE = '1' THEN
registers(to_integer(unsigned(WRITE_REG_SEL))) <= INPUT_VAL; -- Write
IF SEL_REG_A = WRITE_REG_SEL THEN -- Bypass for read A
OUT_REG_A <= INPUT_VAL;
END IF;
IF regBSel = writeRegSel THEN -- Bypass for read B
outB <= input;
IF SEL_REG_B = WRITE_REG_SEL THEN -- Bypass for read B
OUT_REG_B <= INPUT_VAL;
END IF;
END IF;
END IF;
END PROCESS;
END behavioral;
END Behavioral;
6 changes: 3 additions & 3 deletions clkr/Top.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY Top IS
ENTITY TOP IS
PORT (INPUT_CLK : IN STD_LOGIC_VECTOR (0 DOWNTO 0));
END Top;
END TOP;

ARCHITECTURE Behavioral OF Top IS
ARCHITECTURE Behavioral OF TOP IS

-- RAM signals
SIGNAL RAM_ADDR : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0000100";
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Binary file modified clkr/Top_isim_beh.wdb
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28 changes: 16 additions & 12 deletions clkr/clkr.xise
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Expand Up @@ -24,9 +24,13 @@
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="RegFile.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="RamInit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
</files>

<properties>
Expand Down Expand Up @@ -132,9 +136,9 @@
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|Top|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|TOP|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="Top.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/Top" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/TOP" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
Expand Down Expand Up @@ -192,7 +196,7 @@
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="Top" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="TOP" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
Expand All @@ -204,10 +208,10 @@
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="Top_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="Top_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="Top_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="Top_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="TOP_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="TOP_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="TOP_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="TOP_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
Expand Down Expand Up @@ -251,8 +255,8 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/Top/RAM_UNT" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.RAM" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/TOP" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.TOP" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
Expand All @@ -268,7 +272,7 @@
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.RAM" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.TOP" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
Expand Down Expand Up @@ -317,7 +321,7 @@
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|Top|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|TOP|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="clkr" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
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13 changes: 7 additions & 6 deletions clkr/fuse.log
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Running: C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\fuse.exe -intstyle ise -incremental -o C:/Users/sina/Desktop/HyperDbg/clkr/Top_isim_beh.exe -prj C:/Users/sina/Desktop/HyperDbg/clkr/Top_beh.prj Top
Running: C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\fuse.exe -intstyle ise -incremental -o C:/Users/sina/Desktop/HyperDbg/clkr/clkr/TOP_isim_beh.exe -prj C:/Users/sina/Desktop/HyperDbg/clkr/clkr/TOP_beh.prj work.TOP
ISim P.20131013 (signature 0x7708f090)
Number of CPUs detected in this system: 8
Turning on mult-threading, number of parallel sub-compilation jobs: 16
Determining compilation order of HDL files
Parsing VHDL file "C:/Users/sina/Desktop/HyperDbg/clkr/RAM.vhd" into library work
Parsing VHDL file "C:/Users/sina/Desktop/HyperDbg/clkr/Top.vhd" into library work
Parsing VHDL file "C:/Users/sina/Desktop/HyperDbg/clkr/clkr/RAM.vhd" into library work
Parsing VHDL file "C:/Users/sina/Desktop/HyperDbg/clkr/clkr/Top.vhd" into library work
Starting static elaboration
Completed static elaboration
Compiling package standard
Expand All @@ -13,7 +13,8 @@ Compiling package numeric_std
Compiling architecture behavioral of entity RAM [ram_default]
Compiling architecture behavioral of entity top
Time Resolution for simulation is 1ps.
Waiting for 1 sub-compilation(s) to finish...
Compiled 6 VHDL Units
Built simulation executable C:/Users/sina/Desktop/HyperDbg/clkr/Top_isim_beh.exe
Fuse Memory Usage: 36832 KB
Fuse CPU Usage: 593 ms
Built simulation executable C:/Users/sina/Desktop/HyperDbg/clkr/clkr/TOP_isim_beh.exe
Fuse Memory Usage: 36584 KB
Fuse CPU Usage: 546 ms
2 changes: 1 addition & 1 deletion clkr/fuseRelaunch.cmd
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-intstyle "ise" -incremental -o "C:/Users/sina/Desktop/HyperDbg/clkr/Top_isim_beh.exe" -prj "C:/Users/sina/Desktop/HyperDbg/clkr/Top_beh.prj" "Top"
-intstyle "ise" -incremental -o "C:/Users/sina/Desktop/HyperDbg/clkr/clkr/TOP_isim_beh.exe" -prj "C:/Users/sina/Desktop/HyperDbg/clkr/clkr/TOP_beh.prj" "work.TOP"
2 changes: 1 addition & 1 deletion clkr/isim.log
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ISim log file
Running: C:\Users\sina\Desktop\HyperDbg\clkr\Top_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb C:/Users/sina/Desktop/HyperDbg/clkr/Top_isim_beh.wdb
Running: C:\Users\sina\Desktop\HyperDbg\clkr\clkr\TOP_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb C:/Users/sina/Desktop/HyperDbg/clkr/clkr/TOP_isim_beh.wdb
ISim P.20131013 (signature 0x7708f090)
----------------------------------------------------------------------
INFO:Security:51 - The XILINXD_LICENSE_FILE environment variable is not set.
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