Add a project settings file

[EverythingElseWasAlreadyTaken]

Add a project settings file in the folder to keep general information about the project, like the specified language.
Because currently you always have to specify the language for VHDL projects, if you run any FABulous command, because Verilog is always set as default even if you have created a VHDL project.

This project settings file could be based on python-dotenv. So the values can either be set via environment vars as well as a persistent .env file, which also could be automatically created at project creation.

[EverythingElseWasAlreadyTaken]

Fixed with #211