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This repository has been archived by the owner on Oct 13, 2020. It is now read-only.

Releases: CSpyridakis/Tomasulo

Milestone-3

07 Feb 10:03
9715ef2
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-Milestone-3:

  • Reorder Buffer implementation
  • Timing Diagram created

Milestone-2

12 Nov 19:39
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-Milestone-2:
* Tomasulo (Top Module implementation)
* RS testbench and simulation updated (I-type)
* ISSUE testbench and simulation updated
* RF testbench and simulation updated

Milestone-1b

29 Oct 18:49
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-Milestone-1b:
* ISSUE unit implemented
* RS unit implemented
* FU unit implemented
* CDB unit implemented
* RF unit implemented

Milestone-1

22 Oct 09:45
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Milestone-1a:
* I/O connections specified for each unit
* Diagrams for each individual unit
* Top Diagram
* Report explaining above