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Bump axi version
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luca-valente committed Nov 17, 2022
1 parent e2f7fb8 commit 236d251
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2 changes: 1 addition & 1 deletion Bender.yml
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Expand Up @@ -19,7 +19,7 @@ dependencies:
icache_private: { git: "https://github.com/AlSaqr-platform/icache_private.git", rev: "84436443d3a2dbad0b94a85c2c5cc8915632fd26" }
cluster_peripherals: { git: "https://github.com/pulp-platform/cluster_peripherals.git", version: 2.1.0 }
fpu_interco: { git: "https://github.com/pulp-platform/fpu_interco.git", rev: "d217d616bccf53b2f97e766b8cf95fc7c8f87546" }
axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.29.1 }
axi: { git: "https://github.com/pulp-platform/axi.git", rev: "a25b415958e83e232096aa3863da56887abd5991" }
timer_unit: { git: "https://github.com/pulp-platform/timer_unit.git", version: 1.0.2 }
common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.13.1 }
tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.4 }
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1 change: 1 addition & 0 deletions rtl/cluster_bus_wrap.sv
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Expand Up @@ -138,6 +138,7 @@ module cluster_bus_wrap
FallThrough: 1'b0, //Use the reccomended default config
LatencyMode: axi_pkg::NO_LATENCY, // CUT_ALL_AX | axi_pkg::DemuxW,
AxiIdWidthSlvPorts: AXI_ID_IN_WIDTH,
PipelineStages: 32'd0,
AxiIdUsedSlvPorts: AXI_ID_IN_WIDTH,
UniqueIds: 1'b0,
AxiAddrWidth: AXI_ADDR_WIDTH,
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